tag: EDA

Foundry Wars, Take Two
By Ed Sperling - 25 May, 2017 - Comments: 0

Samsung, GlobalFoundries, TSMC and Intel all have declared their intention to fill in nearly every node possible with multiple processes, different packaging options, and new materials. In fact, the only number that hasn't been taken so far is 9nm. It's not that one foundry's 10nm is the same as another's. Each company defines its nodes differently, and these days comparing nodes is almost m... » read more

Reworking Established Nodes
By Ed Sperling - 24 May, 2017 - Comments: 2

New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void. As with all electronic devices, the focus is on cost-cutting. But because these markets are likely ... » read more

Calibre Evolves Constantly
By Mike Santarini - 11 May, 2017 - Comments: 0

I find it truly amazing that despite the constantly changing tide in the digital IC design industry that some tools have remained in that number 1 spot for over a decade. The three tools that immediately come to mind are Synopsys’ PrimeTime and Design Compiler and Mentor’s Calibre. I remember back when I first started covering the industry in the mid-1990s that Quad Design’s Motive sta... » read more

The Rise Of Parallelism
By Ed Sperling - 27 Apr, 2017 - Comments: 1

Parallel computing is an idea whose time has finally come, but not for the obvious reasons. Parallelism is a computer science concept that is older Moore's Law. In fact, it first appeared in print in a 1958 IBM research memo, in which John Cocke, a mathematician, and Daniel Slotnick, a computer scientist, discussed parallelism in numerical calculations. That was followed eight years later by... » read more

Researchers Learn New Tricks
By Brian Bailey - 27 Apr, 2017 - Comments: 0

There is very little EDA research being done in universities today, except for very narrow fields such as [getkc id="33" kc_name="formal verification"]. It has been a steady decline over quite a long period of time. There are several reasons for this. The first is money. Money has to flow into the universities to pay for the research, and this has to lead to some form of prestige for the est... » read more

Avoiding A $7.7B Chip Design Cost
By Frank Schirrmeister - 27 Apr, 2017 - Comments: 0

For years, the story about semiconductor development cost and about EDA contributions has been pretty simple. Cost has been, is, and will likely be for a while, the single biggest issue in scaling development for more complex designs. The next big leap for verification productivity will be the close integration of verification and design engines, both vertically and horizontally as I have writt... » read more

54th DAC Program Finalized
By Michael MacNamara - 11 Apr, 2017 - Comments: 0

A DAC winter meeting held in sunny Mexico isn’t what it’s cracked up to be. (Although we did enjoy the break from this winter storms!) Everybody thinks the Executive Committee members are lounging on the beach enjoying drinks with little umbrellas in them. That couldn’t be further from the truth! In fact, I and 15 other EC members spent most of our February meetings in Puerto Vallar... » read more

HBM Upstages DDR In Bandwidth, Power
By Ann Mutschler - 30 Mar, 2017 - Comments: 1

For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Carving Up Verification
By Ed Sperling - 23 Mar, 2017 - Comments: 0

Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

Antenna Design Grows Up
By Ann Mutschler - 09 Mar, 2017 - Comments: 2

Apple’s iPhone 4 antenna issue represents a classic example of what can go wrong in modern antenna design. Put one in the wrong place, and a seemingly insignificant part can turn a cool new product into a public relations nightmare. Ever since antennas dropped out of sight, most consumers don't give them a second thought. In the 1960s, almost every home had a rooftop antenna. Fast forward ... » read more

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