tag: GlobalFoundries

The Week In Review: Design
By Jesse Allen - 02 Dec, 2016 - Comments: 0

Deals Kilopass extended its deal with ICScape, which makes a Parallel SPICE simulator, for eNVM IP at advanced finFET nodes. Kilopass has been working with ICScape for the past couple of years as part of its qualification methodology. IP Silvaco released three MIPI I3C sensor controller IP cores. Developed with NXP to push adoption of I3C, the new products are an Advanced Slave core wi... » read more

Blog Review: Nov. 30
By Jesse Allen - 30 Nov, 2016 - Comments: 0

Cadence's Paul McLellan presents a three-part series on the future of EDA, with insights from both academia and industry. Mentor's Harry Foster focuses on power management trends in ASIC design, in the latest installment of the 2016 Wilson Research Group verification study. Plus, what aspects of power are verified and how designers describe power intent. Synopsys' Robert Vamosi reports th... » read more

Multi-Patterning Issues At 7nm, 5nm
By Ed Sperling - 28 Nov, 2016 - Comments: 13

Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 25 Nov, 2016 - Comments: 0

R&D Amid budget cuts in the U.S. government, federal funding for R&D at higher education institutions in the United States declined for a fourth straight year, according to a new report from the National Center for Science and Engineering Statistics (NCSES). Overall, universities reported $68.8 billion in R&D expenditures in 2015, a 2.2% increase from 2014, according to the NCSES, part of t... » read more

Can We Measure Next-Gen FinFETs?
By Mark LaPedus - 21 Nov, 2016 - Comments: 6

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 18 Nov, 2016 - Comments: 0

Chipmakers Next month, GlobalFoundries will host a job fair in Portland, Ore., according to reports. The company hopes to hire former Intel workers. These are workers who lost their jobs as part of Intel's recent layoff. Anokiwave, a developer of chips for the mmWave market, has announced a foundry alliance with GlobalFoundries. GlobalFoundries will make so-called Silicon Core chips on a f... » read more

Advanced Packaging Requires Better Yield
By Ed Sperling - 17 Nov, 2016 - Comments: 1

Whether Moore's Laws truly ends, or whether the semiconductor industry reaches into the Angstrom world after 3nm—the semiconductor industry dislikes fractions—advanced packaging increasingly will dominate semiconductor designs. Apple already is on board with its iPhone 7, using TSMC's fan-out approach. And all of the major foundries and OSATs are lining up with a long list of capabilitie... » read more

More EUV Mask Gaps
By Mark LaPedus - 17 Nov, 2016 - Comments: 12

Extreme ultraviolet (EUV) lithography is at a critical juncture. After several delays and glitches, [gettech id="31045" comment="EUV"] is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again. First, the EUV source must generate more ... » read more

Making 2.5D, Fan-Outs Cheaper
By Ed Sperling - 17 Nov, 2016 - Comments: 2

Now that it has been shown to work, the race is on to make advanced [getkc id="27" kc_name="packaging"] more affordable. While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it. At the center o... » read more

Why EUV Is So Difficult
By Mark LaPedus - 17 Nov, 2016 - Comments: 23

For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding. More recently, though, [gettech id="31045" comment="EUV"] lithography appears to be inching closer to pos... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy