tag: IP

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 28 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

Exclusive Research: What’s Happening With Third-Party IP
By Ed Sperling - 27 Mar, 2009 - Comments: 0

Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP. While it’s too early to tell this year what effect that will have on overall design activity—the economy is the rea... » read more

Verifying Low-Power IP And Designs
By Ed Sperling - 13 Mar, 2009 - Comments: 0

By Ed Sperling Verification has always been the time-consuming part of designs. Even at 120nm and above, where power wasn’t much of an issue, verification accounted for an estimated 70 percent of the non-recurring engineering expense in a chip. Since then, the tools to automate design have become more effective, but the complexity of designs has grown by leaps and bounds beyond those tools.... » read more

Next Steps In Verification IP
By Ann Mutschler - 19 Feb, 2009 - Comments: 0

By Ann Steffora Mutschler With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC. In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compoundi... » read more

Making A Multicore System Work
By Ed Sperling - 29 Jan, 2009 - Comments: 0

If you think designing a single-core system is hard, designing multicore systems is multiple times harder. Connecting all the pieces together and making them work properly, if not together, is one of the hardest tasks design engineers and architects will ever face. System-Level Design tracked down some of the experts in this field and sat them down around a table to discuss what’s going... » read more

IP Consolidation Improves Reliability
By Ann Mutschler - 22 Jan, 2009 - Comments: 0

By Ann Steffora Mutschler As individual blocks of IP in an IC design grow to more than 1 million gates, making sure each block functions reliably and interfaces with the system properly is a make-or-break scenario for many companies. For one thing, getting it right is absolutely critical as the semiconductor industry reaches its maturity point with margins harder to reach. Coupled with an ind... » read more

Moving Up The Food Chain
By Ed Sperling - 17 Dec, 2008 - Comments: 0

By Ed Sperling It used to be considered axiomatic that chip companies would be rewarded for spectacular technology, reflected in the market value of their components and in their stock price. But with stock prices routinely getting hammered even before the downturn, many companies have begun to re-think their mission. National Semiconductor, for one, is looking at creating modules rather than... » read more

Better Ways to Connect IP
By Ed Sperling - 20 Nov, 2008 - Comments: 0

By Ed Sperling Re-usable intellectual property may sound great on paper, but actually getting pieces to be as interchangeable as Lego parts and automatically configuring them to work in a system on a chip requires more than technology. It requires a leap of faith on the part of chip engineers, and that doesn’t happen overnight. The first step toward providing the tools was creation of the ... » read more

Special Report: Semiconductor Road Map Survey
By Ed Sperling - 06 Nov, 2008 - Comments: 0

By Ed Sperling The upcoming semiconductor industry road map, which sets up the industry’s strategy and identifies trends for the next 15 years, is filled with three very interesting shifts and gaps. The road map, which will be formally unveiled next month, consists of findings gleaned from all the top chip companies. Juan-Antonio Carballo, a partner at IBM Venture Capital Group who spea... » read more

Quality time?
By Ed Sperling - 08 Oct, 2008 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional design and verification tools and methodology manager at Freescale; Kelly Larson, design verification engineering manager at MediaTek Wireless; Adnan Hamid, CEO of Breker, and ... » read more

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