Power Estimation: Early Warning System Or False Alarm?


Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kulkarni, senior vice president and general m... » read more

The Week In Review: Design/IoT


M&A Mentor Graphics acquired the rest of Calypto. In 2011, Mentor sold Calypto their high-level synthesis solution – Catapult – in exchange for 51% of the company, but left it as a fully standalone entity. Calypto will now be merged into Mentor as a standalone business unit. Tools Synopsys released its HAPS-80 FPGA-based prototyping system. According to Synopsys, the system pro... » read more

Blog Review: Sept. 16


Ansys' Justin Nescott presents five top engineering articles for the week. Being an amateur photography buff, I start salivating at a 250 megapixel camera. Plus, origami and the art of structural engineering and a football-playing robot. Synopsys' Michael Posner provides some shocking information about the buildup of static electricity and the impact it can have on 28nm designs. Increasin... » read more

Appetite For Services Grows


Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more techniques, languages and methodologies that engineers need to learn to be productive in the finFET generation. The services business typically acts as a bridge between down and up cycles in the c... » read more

The Week In Review: Design/IoT


Tools Mentor Graphics rolled out a new version of its tool for transferring PCB designs into data for fabrication, assembly and test. The company also announced that its debug environment will support the UPF Low Power Successive Refinement Methodology. Deals Ansys and Cray are claiming the world's record for simulation by scaling 129,000 cores. That's about 4X the previous record.  Ansys... » read more

Deciphering Performance Analysis


Simulation traditionally has been the go-to technology for improving system performance, but practices are evolving and maturing because engineering teams need to be able to simulate in multiple domains and at at multiple levels of abstraction. In addition, they need to tune the level of [getkc id="11" kc_name="simulation"] they are using to what types of models they have available, and what ki... » read more

Power Estimation: Early Warning System Or False Alarm?


Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kulkarni, senior vice president and general m... » read more

Shift In Focus For Low Power Design


The increased levels of interest we have seen over the last couple of years in system-level power modeling and energy-aware system-level design methodology, coupled with broad participation in the associated industry standard activities around system level power, gives us a clear indication that a shift in focus for low-power design is taking place. Our attempts to deliver energy-efficient high... » read more

Anatomy Of The HDMI IP Certification Flow


HDMI IP plays a critical role in enabling HDMI 2.0 features, making 60 frames per second UHD video and audio possible in multimedia SoCs. SoC designers can avoid costly functionality and interoperability issues by selecting and integrating HDMI IP that has gone through an extensive multi-phase testing process and achieved certification. This white paper outlines the HDMI IP certification flow f... » read more

Blog Review: Sept. 9


Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

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