tag: Synopsys

How Long Will FinFETs Last?
By Ann Mutschler - 13 Aug, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22865" e_name="Samsung"]; and Vic... » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

Using Automotive-Ready IP To Accelerate SoC Development
By Ron DiGiuseppe - 13 Aug, 2015 - Comments: 0

IP suppliers play a key role in the automotive supply chain to enable high-performance advanced driver assistance system (ADAS) SoCs. Vision-based SoCs may contain a high amount of third-party IP to implement the key embedded vision, sensor fusion, multimedia, security and advanced connectivity functions. And while IP suppliers have permeated the semiconductor ecosystem for consumer, mobile, PC... » read more

Power Hungry?
By Synopsys - 12 Aug, 2015 - Comments: 0

Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distributi... » read more

Making Hardware Design More Agile
By Ed Sperling - 12 Aug, 2015 - Comments: 1

Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 10 Aug, 2015 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

The Week In Review: Design/IoT
By Jesse Allen - 07 Aug, 2015 - Comments: 0

Tools Cadence unveiled Joules, its new RTL power analysis solution. The tool performs design synthesis using a new integrated prototype mode of Cadence's Genus Synthesis product, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation. IP Synopsys and ASMedia completed a successful interoperability demonstration of Synopsys' USB 3.1 Devi... » read more

How IoE Will Alter Supply Chains
By Ernest Worthman - 06 Aug, 2015 - Comments: 0

Globalization is a double-edged sword. Without a doubt, it nourishes competition, offers a plethora of independent sources, and bounty of supplies from a global pool of vendors. That is the good side. The downside is that control becomes a management nightmare. Well-oiled, traditional supply chains systems will have to be redesigned to function across a variety of variables that can interrupt t... » read more

Blog Review: Aug. 5
By Jesse Allen - 05 Aug, 2015 - Comments: 0

Fresh from the July 2015 Type-C InterOp Event, where USB engineers wheel a prototype on a cart from hotel room to hotel room, testing interoperability, Synopsys' Morten Christiansen says Type-C has arrived. Mentor's Colin Walls discusses the reasons to tackle embedded software development with a bottom-up approach. In their latest video, Cadence's Kishore Kasamsetty discusses why choose L... » read more

Multiple Lithography Options Still Remain in Play
By Paula Doe - 03 Aug, 2015 - Comments: 1

The throughput and uptime of EUV, and the overlay accuracy of 193nm immersion lithography, continue to steadily improve, though neither is yet ready for 10nm production, according to speakers at SEMICON West. Mike Lercel, ASML director, Product Marketing, reported several EUV tool sites achieved 70 percent uptime for more than a week, and one customer site had done so for more than four ... » read more

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