Chip Industry Week in Review


Texas Instruments will invest more than $60 billion to build and expand seven semiconductor fabs in Texas and Utah, supporting more than 60,000 U.S. jobs. Chinese automakers — including SAIC Motor, Changan, Great Wall Motor, BYD, Li Auto and Geely — are aiming to launch new models with 100% homemade chips, some as early as 2026, reports Nikkei Asia. Marvell introduced 2nm custom SRAM ... » read more

Power Delivery Challenges For AI Chips


As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

Improving Fab Engineering Efficiency With Autonomous Data Analytics


During my earlier career as a process integration engineer, one of my primary responsibilities was to find yield enhancement opportunities by investigating underlying relationships between bin failures and process parameters within the fab. While performing this analysis, there were many impediments to identifying relationships among different data types: sort maps, electrical test maps, parame... » read more

Are Larger Reticle Sizes On The Horizon?


Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

Can You Build A Known-Good Multi-Die System?


Semiconductor Engineering sat down to discuss the challenges of designing and testing multi-die systems, including how to ensure they will work as expected, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadenc... » read more

Blog Review: June 18


Synopsys’ John Koeter and other industry experts discuss whether high-bandwidth memory should follow established standards for broad compatibility and scalability or be customized to address specific use case requirements and time-to-market targets. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about how progress in 3D-IC development, thermal management, and the indu... » read more

Chip Industry Week in Review


The Chinese Academy of Sciences unveiled a fully automated processor chip design system, claiming the potential to accelerate semiconductor development and replace human programmers. Micron Technology plans to expand its U.S. investments to approximately $150 billion in domestic memory manufacturing and $50 billion in R&D, which is $30 billion higher than previously reported. AMD laun... » read more

Industry Leaders Provide Insights And Guidance On Multi-Die Designs


Multi-die designs seamlessly integrate multiple heterogeneous or homogeneous dies in a single package to significantly enhance chip performance and efficiency — making them indispensable for high-performance computing (HPC), artificial intelligence (AI), data analytics, advanced graphics processing, and other demanding applications. While representing a groundbreaking leap forward, multi-d... » read more

RISC-V’s Increasing Influence


The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary to move forward gradually. Computer architectures and software have followed in the footsteps of processors developed 80 years ago. They aimed to solve sequential, scalar arithmetic problems usin... » read more

Multi-Die Assemblies Complicate Parasitic Extraction


The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

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