tag: SystemC

The Next Level Of Abstraction For System Design
By Frank Schirrmeister - 24 Sep, 2015 - Comments: 1

Recently there have been a lot of discussions again about the next level of design abstraction for chip design. Are we there yet? Will we ever get there? Is it SystemC? UML/SysML perhaps? I am taking the approach of simply claiming victory: Over the last 20 years we have moved up beyond RTL in various areas—just in a fragmented way. However, the human limitations on our capacity for processin... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

A Comparison Of Embedded Non-Volatile Memory Technologies And Their Applications
By Kilopass - 07 May, 2015 - Comments: 0

With complexity of SOCs growing and time to market cycles shortening, designers need to have an arsenal of tricks to deliver highly differentiated products to market quickly. The arsenal may include SystemC, EDA tools to achieve a faster timing closure, and IP from high speed I/Os to memories. The most pervasive memory IPs are SRAM and ROM. Less pervasive memory IPs include non-volatile memory ... » read more

Is SystemC Broken?
By Brian Bailey - 26 Mar, 2015 - Comments: 19

In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry needs a viable [getkc id="104" kc_name="virtual prototype"]. That requires a suitable language in order to express necessary concepts at a high enough level of [getkc id="101" kc_name="abstraction"] s... » read more

Design By Architect Or Committee?
By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

An Update On The IEEE 1801-2013 Unified Power Format Standard
By Barry Pangrle - 09 Feb, 2015 - Comments: 0

It’s been almost six years since the first IEEE 1801 standard was officially published in March of 2009, but the standard can trace its roots back to years before that date. On May 30, 2013 the IEEE released a press announcement for the most recent version of the standard, IEEE 1801-2013 (a.k.a. UPF 2.1). This brought forward a standard for the industry that is finally backed by all of the ma... » read more

Tools And Flows In 2015
By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Simulation Performance Driven By Model Efficiency
By Jon McDonald - 29 Jan, 2015 - Comments: 0

In real estate it’s all about location, location, location. For system level simulation it’s all about performance, performance, performance. I have heard many opinions on the performance of SystemC and TLM simulations: some positive, some negative, much of the opinion based on hearsay or other unreliable information. I believe the performance of the simulation is mainly driven by the model... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 06 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down with Barry Spotts, senior core competency FAE for fabric and tools at [getentity id="22186" comment="ARM"]; Vasan Karighattam, senior director of architecture for SoC and SSW engineering at [getentity id="22664" e_name="Open-Silicon"]; Tom De Schutter, senior product marketing manager for Virtualizer Solutions at [getentity id="22035" e_name="Synopsys"]; Larry... » read more

How Many Levels Of Abstraction Are Needed?
By Jon McDonald - 23 Oct, 2014 - Comments: 0

Recently I was having a conversation with a user who was creating cycle accurate SystemC models. My initial thought was, "Why would this be necessary?" Through the course of discussions I realized that he did have a design questions that required that level of accuracy and the simulation performance trade-offs were appropriate for his needs. His cycle accurate SystemC models were running at abo... » read more

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