tag: verification

The Double Whammy
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

Verify This
By Frank Ferro - 23 Aug, 2012 - Comments: 0

By Frank Ferro Verify this? No, New Jersey in me is not coming out. This is not a pejorative; it is simply a request and a question. It is a request by SoC designers to the verification team. It is also the verification’s team response when they realize the enormity of the task: “You want me to verify this?” As I continue the discussion on the use of System IP for SoC design, one of ... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?
By Various Writers - 23 Aug, 2012 - Comments: 0

It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more

RTL Power Reduction Triathlon
By Atrenta - 09 Aug, 2012 - Comments: 0

Unless you’ve just come out of a week-long coma, you’ve been watching at least part of the Olympic Games in London. The years of training, the drama of competition, the thrill of victory… (you know the rest). Some contests come down to the smallest of margins to define who wins gold. The recent women’s triathlon is one such case. After a 500-meter swim, a 43-kilometer bike ride and a 10... » read more

Experts At The Table: Pain Points
By Ed Sperling - 27 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: What comes next requires a lot of guesswork in the design, do... » read more

Lint Your Hardware Description: The Need To Be Fast, Accurate, Scalable And Flexible
By Various Writers - 14 Jun, 2012 - Comments: 0

A reliable linting tool must be SAFE (Scalable, Accurate, Fast and Extendible) so it can help catch issues early in the design cycle - issues that may be missed by traditional dynamic verification techniques. The main objective of a SAFE linting solution is to reduce costly design iterations, prevent late stage design ECOs and promote seamless reuse of IPs. Such a linting solution will need to ... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 09 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 22 Feb, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wha... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 17 Feb, 2012 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy