tag: verification

Verification Of Multi-Clock Designs: The Bigger Picture
By Various Writers - 19 Nov, 2009 - Comments: 0

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this is further complicated by multiple modes of operation and the associated range of clocking scenarios. This leads to ever increasing numbers of clock interfaces, where data is transferred betw... » read more

Verify, Verify, Verify
By Ed Sperling - 02 Oct, 2009 - Comments: 0

Verification has claimed the biggest chunk of design time and cost for many generations of chips, but it has now been elevated from design headache to the poster child of what’s ailing semiconductor design. The question being asked in many quarters, and also in many different ways, isn’t whether the verification approach and tools are right. It’s whether the fundamentals of design an... » read more

Verification As A Deterrent?
By Ed Sperling - 24 Sep, 2009 - Comments: 0

By Ed Sperling Verification is becoming more than a bottleneck in semiconductor design. It’s actually deterring companies from adopting the latest techniques for saving power or building certain features into chips. The problem is one of complexity, and it’s getting worse at every node. While the tools exist to do complex designs, there are the classic tradeoffs of area, power and per... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

The Next Problem In Verification
By Ed Sperling - 14 May, 2009 - Comments: 0

Last week’s blog on OVM vs. VMM was like a match on dry timber, which is probably a bad analogy to make in California these days. Weeding through the comments—both on the record and off, and there was plenty more off the record—it appears there’s plenty of work under way to bridge the two worlds, but there’s an inverse amount of information available to the people who use one or the... » read more

VMM vs. OVM Becomes More Important
By Ed Sperling - 07 May, 2009 - Comments: 0

For all the talk about VMM vs. OVM and how it doesn’t matter…well, apparently it does.   It’s not that one verification environment is so much better than the other. That’s like saying one religion is better than another. People kill each other over those kinds of statements. And the truth is, there are plenty of people who will argue for and against each side.   Strangely, when... » read more

Intelligent Verification Offers Hope For “Smartening” Up Verification
By Cheryl Ajluni - 28 Apr, 2009 - Comments: 0

By Cheryl Ajluni As with death and taxes, when it comes to design some things are just inevitable. For one, as design geometries shrink, design complexity will continue to increase. For another, verification is the single most time-consuming and intensive part of the entire design cycle. While new tools and methodologies have enabled designers to work through many of the existing complexity i... » read more

Next Steps In Verification IP
By Ann Mutschler - 19 Feb, 2009 - Comments: 0

By Ann Steffora Mutschler With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC. In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compoundi... » read more

Houston…We Have A System-Level Problem
By Ed Sperling - 04 Dec, 2008 - Comments: 0

[youtube vid=iZ61OU12TNU] Just imagine what happens when the guidance system on the International Space Station goes on the fritz and the entire lab begins doing somersaults through outer space. Then the solar panels no longer work and the communication system fails, and suddenly you understand how serious system-level design problems can become. Ret. Capt. Daniel Bursch recounts the inciden... » read more

OVM vs. VMM: What’s Next?
By Ed Sperling - 23 Oct, 2008 - Comments: 0

By Ed Sperling The lines are drawn. On one side stand Mentor Graphics and Cadence. On the other are Synopsys and ARM. And caught in the middle are verification engineers, with a preference for one or the other and often in mixed verification teams. The battle for dominance between the Verification Methodology Language (VMM) and the Open Verification Methodology (Open Verification Methodology)... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy