tag: Accellera

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

Gaps Emerging In System Integration
By Brian Bailey - 29 Jun, 2020 - Comments: 0

The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

Standard Evolution
By Brian Bailey - 26 Mar, 2020 - Comments: 0

I recently had the opportunity to sit down with Lu Dai, chairman of Accellera Systems Initiative and senior director of engineering for Qualcomm. SE: I have noticed a change in the way that Accellera operates these days. In the past, standards were driven by the EDA companies, but recently we have seen a lot more end-user company involvement and they are the companies driving new standards. ... » read more

Do You Trust Your IP Supplier?
By Brian Bailey - 26 Mar, 2020 - Comments: 0

How much do you trust your IP supplier, regardless of whether IP was developed in-house or by a third-party provider? And what implications does it have a system integrator? These are important questions that many companies are beginning to ask. Today, there are few methods, other than documentation, that provide the necessary information. The software industry may be ahead of the hardware i... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Feb, 2020 - Comments: 0

Tools Synopsys debuted the VC SpyGlass RTL Static Signoff platform featuring new noise reduction technology that uses machine learning to reduce noise by 10X without loss of quality of results. It also provides comprehensive CDC and RDC analysis to catch logic issues added during implementation, and is integrated with Synopsys' automated debug system. Ansys released RaptorH, a tool that com... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 28 Feb, 2020 - Comments: 0

AI/Edge The United States Department of Defense (DOD) has adopted ethical principles for using artificial intelligence in warfare that chiefly say the U.S. has to follow the laws, treaties, in use of AI in warfare. Any AI used by DOD has to be responsible, equitable, traceable, reliable and governable. “The Department will design and engineer AI capabilities to fulfill their intended functio... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 21 Feb, 2020 - Comments: 0

AI The European Union put out a white paper about artificial intelligence. The United States Chief Technology Officer Michael Kratsios criticized the EU stance on Thursday as clumsy. "We found, what they actually put out yesterday, really, I think, in some ways clumsily attempts to bucket AI-powered technologies as either ‘high-risk’ or ‘not high-risk,’” he said, according to a news ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Feb, 2020 - Comments: 0

Dialog Semiconductor will acquire Adesto Technologies for $12.55 per share in cash, or for approximately $500 million enterprise value. Founded in 2006 and based in Santa Clara, CA, Adesto provides application-specific semiconductors, embedded systems, and specialty memory for IoT and industrial IoT applications. “This acquisition substantially enhances our position in the Industrial IoT mark... » read more

Reducing Power At RTL
By Ann Mutschler - 13 Feb, 2020 - Comments: 0

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on interactions with other components. This has been a growing problem in leading-edge designs for the past couple of process nodes, but similar issues have begun creeping into less-sophisticated designs as... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Nov, 2019 - Comments: 1

Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

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