tag: ANSYS

Chip Industry Week in Review
By The SE Staff - 30 May, 2025 - Comments: 1

The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI
By Ed Sperling - 29 May, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

Blog Review: May 28
By Jesse Allen - 28 May, 2025 - Comments: 0

Siemens’ Patrick Hope considers how to fully perform post-route signal integrity verification on PCB designs while maintaining the project’s timeline by implementing a progressive verification methodology that enables signal integrity experts to focus on issues that demand their expertise rather than simple errors. Cadence’s Vanessa Do checks out how CXL addresses the constant demand f... » read more

Blog Review: May 21
By Jesse Allen - 21 May, 2025 - Comments: 0

Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

Development Flows For Chiplets
By Brian Bailey - 15 May, 2025 - Comments: 2

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These ear... » read more

How To Optimize Products For Performance And Sustainability
By Mehru Singh - 15 May, 2025 - Comments: 0

By Mehru Singh and Tim Ebdon Developing sustainable products is key to a company's success. From complying with regulatory requirements and meeting corporate net-zero goals to providing a superior consumer experience and reducing costs, a company’s ability to design, develop, manufacture, and source parts and components sustainably strengthens its market position. While companies have deve... » read more

Blog Review: May 14
By Jesse Allen - 14 May, 2025 - Comments: 0

Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

E-Powertrain EMC Design And Validation
By Ansys - 14 May, 2025 - Comments: 0

In the pursuit of zero-emission vehicles, the design of the e-powertrain and its electronic systems encounters numerous challenges. From stringent regulatory requirements to the demand for enhanced performance and efficiency, the landscape is ripe with complexities. Here, simulation emerges as a vital tool, offering a pathway to navigate these challenges with precision and innovation. What y... » read more

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