tag: ANSYS

New Technologies To Support 3D-ICs
By Brian Bailey - 04 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Blog Review: Sept. 4
By Jesse Allen - 04 Sep, 2019 - Comments: 0

Synopsys' Taylor Armerding checks out Apple's newly expanded bug bounty program, with bounty payouts are increasing to compete with malicious actors, and why even with security-oriented development the practice of bug bounties will remain needed. Mentor's Colin Walls shares a few more embedded software tips, this time on external variables, delay loops in real time systems, and meaningful pa... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Aug, 2019 - Comments: 0

Rambus completed its acquisition of Northwest Logic, a supplier of memory, PCIe and MIPI digital controllers. The Hillsboro, OR office of Northwest Logic will remain in place, along with the entire staff. SureCore launched a new low power design service. The company's offering includes concept-to-tape-out low power mixed-signal design expertise such as design and layout capabilities, technol... » read more

On The Cusp Of 5G
By Kevin Fogarty - 29 Aug, 2019 - Comments: 0

Carriers and chipmakers are celebrating the rollout of the first standards-compliant commercial 5G services. "We are, officially in the era of 5G," said John Smee, vice president of engineering at Qualcomm at the recent 5G Summit at IEEE's International Microwave Symposium (IMS) in Boston. Movement is happening on the commercial end. Major U.S. carriers Verizon, AT&T and Sprint have set ... » read more

Taking Energy Into Account
By Ann Mutschler - 28 Aug, 2019 - Comments: 1

Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

Blog Review: Aug. 28
By Jesse Allen - 28 Aug, 2019 - Comments: 0

Cadence's Paul McLellan takes a look at the numerous challenges in designing and manufacturing Cerebras' massive 400,000 processor, 1.2 trillion transistor chip. Synopsys' Taylor Armerding points to a lack of robust mobile app security and why building in security from the beginning can lead to greater productivity and cost saving. Mentor's Paul Johnston takes a look at what's in store at... » read more

EDA Gears Up For 3D
By Brian Bailey - 26 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Blog Review: Aug. 21
By Jesse Allen - 21 Aug, 2019 - Comments: 0

Cadence's Paul McLellan considers the path to autonomous vehicles and the many barriers that stand in the way. Mentor's Colin Walls notes that the fundamental function of an RTOS is to give the developer control of time and points to some of the time oriented services that assist. Synopsys' Taylor Armerding points to ways the financial services industry could improve cybersecurity, from u... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Aug, 2019 - Comments: 0

Everspin and Seagate inked a patent cross-licensing agreement, including the assignment and licensing of MRAM patents from Seagate to Everspin as well as licensing of specific Tunneling Magnetoresistance (TMR) patents from Everspin to Seagate, which will be used in HDD read/write head technology. Subaru utilized ANSYS' SCADE suite for critical control systems to design and validate embedded ... » read more

GaN Versus Silicon For 5G
By Kevin Fogarty - 15 Aug, 2019 - Comments: 0

The global race to launch 5G mmWave frequencies could provide a long-anticipated market opportunity for gallium nitride (GaN) as an alternative to silicon. GaN is more power-efficient than silicon for 5G RF. In fact, GaN has been the heir apparent to silicon in 5G power amplifiers for years, especially when it comes to mmWave 5G networks. What makes it so attractive is its ability to efficie... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy