tag: ANSYS

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Open ISAs Gaining Traction
By Ann Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

Why Data Is So Difficult To Protect In AI Chips
By Ed Sperling - 25 Sep, 2019 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss a wide range of hardware security issues and possible solutions with Norman Chang, chief technologist for the Semiconductor Business Unit at ANSYS; Helena Handschuh, fellow at Rambus, and Mike Borza, principal security technologist at Synopsys. What follows are excerpts of that conversation. The first part of this discussion ca... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2019 - Comments: 0

Mentor's Dave Rich points out that unexpected values from a constraint solver can often be explained by how Verilog expression evaluation rules affect the solution space of SystemVerilog constraints. Cadence's Madhavi Rao points to the need for new and updated safety and cybersecurity standards for autonomous vehicles and highlights one of the most challenging parts of AV deployment. A Sy... » read more

Blog Review: Sept. 18
By Jesse Allen - 18 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out MLPerf and the challenges involved in developing a benchmark to assess machine learning training and inference performance. Synopsys' Om Prakash Thakur and Nusrat Ali take a look at the different types of NVDIMM and how it can bridge the performance gap between memory and storage solutions in servers. Mentor's Matthew Ballance points to why adoption of P... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Sep, 2019 - Comments: 0

M&A ANSYS will acquire Livermore Software Technology Corp. (LSTC), a provider of explicit dynamics and other advanced finite element analysis technology. Based in Livermore, CA, LSTC was founded in 1987 to commercialize the DYNA3D technology developed at the Lawrence Livermore National Laboratory. DYNA3D became the company's premier product LS-DYNA, a general purpose nonlinear finite eleme... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Reducing Software Power
By Brian Bailey - 12 Sep, 2019 - Comments: 0

With the slowdown of Moore's Law, every decision made in the past must be re-examined to get more performance or lower power for a given function. So far, software has remained relatively unaffected, but it could be an untapped area for optimization and enable significant power reduction. The general consensus is that new applications such as artificial intelligence and machine learning, whe... » read more

Blog Review: Sept. 11
By Jesse Allen - 11 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out the challenges of processing-in-memory and the steps involved in building a logic flow on a DRAM process. Synopsys' Taylor Armerding notes that with safety-critical software an ever-present factor in modern life, it's more necessary than ever to take the time to ensure quality and security when failures can be life-threatening. In a video, Mentor's Colin... » read more

Dell EMC Ready Solutions for HPC Digital Manufacturing – ANSYS Performance
By Ansys - 11 Sep, 2019 - Comments: 0

This technical white paper describes the performance of ANSYS Fluent, Mechanical, and CFX on the Dell EMC Ready Bundle for HPC Digital Manufacturing, which was designed and configured specifically for Digital Manufacturing workloads, where Computer Aided Engineering (CAE) applications are critical for virtual product development. In addition, the architecture of the Dell EMC Ready Bundle for HP... » read more

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