tag: ANSYS

Blog Review: June 26
By Jesse Allen - 26 Jun, 2019 - Comments: 0

Arm's Krish Nathella and Dam Sunwoo dig into research to make a practical implementation of a temporal data prefetcher that overcomes the huge on- and off-chip storage and traffic overheads usually associated with them. Cadence's Paul McLellan notes that while concerns about uncover bias in computer vision algorithms usually focus on people, a team at Facebook found that object recognition t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 21 Jun, 2019 - Comments: 0

ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

Wrestling With High-Speed SerDes
By Ann Mutschler - 19 Jun, 2019 - Comments: 2

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Blog Review: June 19
By Jesse Allen - 19 Jun, 2019 - Comments: 0

Mentor's Rebecca Lord digs into signal integrity complications and why today's high frequency signals make it important to understand the physics of transmission lines. Cadence's Meera Collier points to the need to recognize diversity and nuance when compiling AI training datasets and avoid the oversimplification that can lead to bias. Synopsys' Deepak Nagaria checks out the new features ... » read more

Circuit Aging Becoming A Critical Consideration
By Ann Mutschler - 17 Jun, 2019 - Comments: 5

Circuit aging was considered somebody else's problem when most designs were for chips in consumer applications, but not anymore. Much of this reflects a shift in markets. When most chips were designed for consumer electronics, such as smart phones, designs typically were replaced every couple of years. But with the mobile phone market flattening, and as chips increasingly are used in automot... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Jun, 2019 - Comments: 0

M&A Intel will acquire Barefoot Networks, a maker of programmable Ethernet switch silicon and the P4 networking programming language for data centers. Founded in 2013, the Santa Clara-based company has raised $155.4 million in funding. Terms of the deal were not disclosed, but Intel expects the acquisition to be final in the third quarter of this year. Tools & IP Mentor extended it... » read more

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Blog Review: June 12
By Jesse Allen - 12 Jun, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that city and state governments aren't learning from history when it comes to ransomware, and despite numerous examples of recent attacks are not implementing proper security measures or even keeping systems patched. Cadence's Paul McLellan shares highlights from the recent Embedded Vision Summit, including how light can be used at femtosecond intervals to ob... » read more

Critical Success Factors When Implementing Simulation Led Design Exploration
By Ansys - 12 Jun, 2019 - Comments: 0

Upfront simulation in the design stage of product development has long held great promise. It lets engineers find design flaws earlier and explore more alternatives. There is little doubt that such an effort offers tangible benefits to engineering organizations. But several obstacles often prevent companies from implementing a successful simulation initiative. The knowledge, skill, and time ... » read more

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