Can Startups Solve Today’s Automotive Challenges?


When asked about the most pressing concerns today amongst automotive customers, some leading industry suppliers had the following to say: Samer Hijazi, senior design engineering architect, IP Group at Cadence: How fast can I deploy? Ron DiGiuseppe, Senior Strategic Marketing Manager at Synopsys: Our customers are very broadly requiring ISO26262 safety compliance in our products as well a... » read more

Optimizing Multiple IoT Layers


As the number of connected devices rises, so do questions about how to optimize them for target markets, how to ensure they play nicely together, and how to bring them to market quickly and inexpensively. [getkc id="76" kc_name="IoT"] is broad term that encompasses a lot of disparate pieces for devices, systems, and connected systems. At the highest levels are hardware and software, but with... » read more

Smart Cities, Challenging Issues


Smart cities are coming. Not everything will be connected, and not everything will be connected at once. Still, governments around the globe are beginning to tap into a world of connected devices and sensors for reasons ranging from cheaper lighting to less traffic, lower crime, and improved air quality. Smart cities encompass all manner of usage models and equipment — parking meters, traf... » read more

IoT, Architectures, And Security


Mike Muller, CTO of [getentity id="22186" comment="ARM"], sat down with Semiconductor Engineering to talk about security, IoT market changes, and future technology requirements. What follows are excerpts of that conversation. SE: Security is a growing problem. How do we deal with it? Muller: However fast the world is moving, if you look at fundamental hardware and system design, it’s ru... » read more

Blog Review: Nov. 30


Cadence's Paul McLellan presents a three-part series on the future of EDA, with insights from both academia and industry. Mentor's Harry Foster focuses on power management trends in ASIC design, in the latest installment of the 2016 Wilson Research Group verification study. Plus, what aspects of power are verified and how designers describe power intent. Synopsys' Robert Vamosi reports th... » read more

Multi-Patterning Issues At 7nm, 5nm


Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

Blog Review: Nov. 23


Mentor's Brian Derrick argues that both designers and ecosystems are changing to leverage advances in sensing technology at the edge of the IoT. Cadence's Paul McLellan listens in on a DVCon Europe keynote by NXP's Jürgen Weyer on what automotive is learning from mobile and where the big challenges lie. Synopsys' Tumuluri SantoshaLakshmi talks about seven of the biggest challenges in JED... » read more

Homogeneous And Heterogeneous Computing Collide


Eleven years ago processors stopped scaling due to diminishing returns and the breakdown of [getkc id="213" kc_name="Dennard's Law"]. That set in motion a chain of events from which the industry has still not fully recovered. The transition to homogeneous multi-core processing presented the software side with a problem that they did not know how to solve, namely how to optimize the usage of ... » read more

The Limits Of Parallelism


Parallelism used to be the domain of supercomputers working on weather simulations or plutonium decay. It is now part of the architecture of most SoCs. But just how efficient, effective and widespread has parallelism really become? There is no simple answer to that question. Even for a dual-core implementation of a processor on a chip, results can vary greatly by software application, operat... » read more

Constructing The Pillars Of The ARM HPC Ecosystem


In talking with HPC users at SC15 following the announcement of the OpenHPC project, I consistently heard that while they valued having a common open source framework covering a baseline set of HPC codes, they wanted to see more than one chip architecture represented. This is important when you consider that many HPC users are focused on getting to exascale computing for future supercomputer de... » read more

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