Too Many Standards, But Still Not Enough


By Ed Sperling The semiconductor industry has been one of the most prolific sectors in history when it comes to generating standards. Talk to any design engineer facing time-to-market pressures, new packaging approaches, and a mindboggling number of merchant IP, subsystems and interface requirements, and you’ll hear a compelling pitch for new standards. Talk to his or her boss and you’ll p... » read more

ARM: Bulk ports directly to FD-SOI


In a recent ASN posting, ARM Fellow Jean-Luc Pelloie said that bulk logic designs can be ported directly to fully-depleted (FD)-SOI for high-performing, low-power mobile apps. ARM sees fully-depleted FD-SOI is a potential alternative to BULK 20nm.  Jean-Luc addressed the question of  what sort of impact a port from bulk FD-SOI would  have on the design flow. His answer is: very little. ... » read more

Five Important Changes That Will Affect Power


By Ed Sperling So far most of the energy savings in SoCs have been achieved using two main approaches—turning off most of the chip most of the time, and changing the materials used to insulate against current leakage. Over the next few years, changes to designs will be more radical, encompass more pieces of a bigger system, and they will be orders of magnitude more effective. From a marke... » read more

Power Gating And Power-Centric Programing


By Pallab Chatterjee SoC design has a number of techniques for power management. One of the more prevalent methods is to use power gating to turn on and off blocks based on applications being run, and mode controls. Power gating while being supported by the two major EDA power design flows, UPF and CPF, still has some implementation challenges. The flows have to make sure that the states of... » read more

Innovation At The Core


By Barry Pangrle A number of next-generation ARM-based multi-core systems are starting to show up in the press. Nvidia has released information on its upcoming Tegra 3 (also known as “Kal El”). At last week’s ARM Techcon in Santa Clara, ARM gave several presentations around its Cortex-A7 (Kingfisher) and Cortex-A15 (Eagle) architectures and collectively about its big.LITTLE strategy. Qua... » read more

SOI Conference Shows SOI Driving Key Roadmaps


By Adele Hars The 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at th... » read more

The Next SoCs


By Ed Sperling The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips. System-Level Design asked executives from across the SoC ecosystem what will change, what’s d... » read more

Collaboration Grows


By Ed Sperling A series of recent announcements by the Big Three EDA vendors and their well-known partners from across the disaggregated SoC ecosystem is lending new credence to the impact of collaboration. While IDMs such as Apple, Intel, Samsung and IBM continue to blaze their own trail, developing in-house tools, methodologies, processes and chips, fabless companies working with foundrie... » read more

Experts At The Table: Retrofitting Older Process Nodes


By Ed Sperling Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in... » read more

A Different Kind Of Design


Intel’s announcements at the Intel Developer Forum this week that it will be creating physically smaller packages that can run on far less energy raises some interesting questions about the future of all design. We’ve become accustomed to one-chip implementations, whether that’s a monolithic processor or an SoC with lots of processors. In the future, though, there may be multiple chips, a... » read more

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