tag: Cadence Design Systems

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 24 Jun, 2022 - Comments: 0

Automotive, mobility The U.S. Department of Transportation’s National Highway Traffic Safety Administration (NHTSA) published a notice of proposed rulemaking (NPRM) to change the regulations on event data recorders (EDRs) to extend the EDR recording period for “timed data metrics from 5 seconds of pre-crash data at a frequency of 2 Hz to 20 seconds of pre-crash data at a frequency of 10 Hz... » read more

EDA Embraces Big Data Amid Talent Crunch
By Marie C. Baca - 23 Jun, 2022 - Comments: 0

The semiconductor industry’s labor crunch finally has convinced chip designers to bet big money on big data. As recently as 2016, executives weren’t sure there was a market for big data approaches to electronic design automation. The following year, utilization of big data remained stuck in its infancy. And in 2018, Semiconductor Engineering questioned why the EDA sector wasn’t investi... » read more

Overcoming Signal, Power, And Thermal Challenges Implementing GDDR6 Interfaces
By Cadence - 22 Jun, 2022 - Comments: 0

Graphics processing units (GPUs) and graphics double data rate (GDDR) memory interfaces are essential to graphics cards, game consoles, high-performance computing (HPC), and machine learning applications. These interfaces enable data transfer speeds of over 665GB per second today and will continue to support well over a terabyte per second (TBps) in next-generation GDDR interfaces. Signal integ... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 17 Jun, 2022 - Comments: 0

Automotive, mobility U.S. National Highway Traffic Safety Administration (NHTSA) release its first crash reports from ADAS (advanced driver assistance systems, i.e., SAE Level 2) and ADS (automated driving systems, i.e., SAE Levels 3-5).  The systems had to be in use at least 30 seconds before the crash in order for it to be reportable. The car may have had the system turned off at the time ... » read more

DRAM Thermal Issues Reach Crisis Point
By Karen Heyman - 09 Jun, 2022 - Comments: 5

Within the DRAM world, thermal issues are at a crisis point. At 14nm and below, and in the most advanced packaging schemes, an entirely new metric may be needed to address the multiplier effect of how thermal density increasingly turns minor issues into major problems. A few overheated transistors may not greatly affect reliability, but the heat generated from a few billion transistors does.... » read more

Removing Barriers For End-To-End Analytics
By Anne Meixner - 07 Jun, 2022 - Comments: 0

Parties are coming together, generating guidelines for sharing data from IC design and manufacturing through end of life, setting the stage for true end-to-end analytics. While the promise of big data analytics is well understood, data sharing through the semiconductor supply chain has been stymied by an inability to link together data sources throughout the lifecycle of a chip, package, or ... » read more

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

EDA Software Design Flow Considerations For The RF/Microwave Module Designer
By Cadence - 25 May, 2022 - Comments: 0

Miniaturization of consumer products, aerospace and defense systems, medical devices, and LED arrays has spawned the development of a technology known as the multi-chip module (MCM), which combines multiple integrated circuits (ICs), semiconductor die, and other discrete components within a unifying substrate for use as a single component. This white paper outlines the steps for implementing an... » read more

The Challenge Of Optimizing Chip Architectures For Workloads
By Brian Bailey - 12 May, 2022 - Comments: 1

It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

Improving PPA With AI
By John Koon - 12 May, 2022 - Comments: 0

AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

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