tag: Cadence

The Case For Embedded FPGAs Strengthens And Widens
By Brian Bailey - 25 Apr, 2019 - Comments: 2

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Automotive Functional Safety Using LBIST and Other Detection Methods
By Cadence - 24 Apr, 2019 - Comments: 0

Functional safety requirements for safety-critical applications are addressed with the insertion of safety mechanisms to detect and/or correct potential failures: their effectiveness is measured by diagnostic coverage (DC). Built-in-self-test, or BIST, originally developed for manufacturing test, can be used as a detection mechanism for functional safety. However, it requires original values to... » read more

Blog Review: April 24
By Jesse Allen - 24 Apr, 2019 - Comments: 0

Rambus' Steven Woo checks out changes in the hardware used for neural network training and the importance of co-design of hardware and software. Cadence's Meera Collier makes an argument for why vehicle sensors watching the driver could prevent some distraction and fatigue-related crashes. Synopsys' Dan Lyon and Garrett Sipple point to some best practices for how to deal with a changing t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Apr, 2019 - Comments: 0

Intel acquired vision and video FPGA IP company Omnitek. Founded in 1998, the Basingstoke, England-based company has produced FPGA IP cores for video processing including conversion and enhancement, creating arbitrary image warps on a real time video stream, connectivity, and deep learning and AI inferencing. Terms of the deal were not disclosed. Qualcomm and Apple have dropped all litigatio... » read more

Designing For The Edge
By Ann Mutschler - 17 Apr, 2019 - Comments: 0

Chip and system architectures are beginning to change as the tech industry comes to grips with the need to process more data locally for latency, safety, and privacy/security reasons. The emergence of the intelligent edge is an effort to take raw data from endpoints, extract the data that requires immediate action, and forward other data to various local, regional or commercial clouds. The b... » read more

The Role Of EDA In AI
By Brian Bailey - 17 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Blog Review: April 17
By Jesse Allen - 17 Apr, 2019 - Comments: 0

In a video, Mentor's Colin Walls digs into power management in embedded software with a particular look at the Power Pyramid model. Synopsys' Taylor Armerding checks out the state of application security at this year's RSA and finds that while organizations are paying attention to security through training and dedicated teams, roadblocks still remain. Cadence's Paul McLellan considers how... » read more

Target: 50% Reduction In Memory Power
By Brian Bailey - 11 Apr, 2019 - Comments: 3

Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Low Power Meets Variability At 7/5nm
By Ann Mutschler - 11 Apr, 2019 - Comments: 0

Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Optimization Challenges For Safety And Security
By Brian Bailey - 11 Apr, 2019 - Comments: 0

Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together. Design teams are now dealing with the impl... » read more

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