tag: Cadence

The Week In Review: Design/IoT
By Jesse Allen - 18 Sep, 2015 - Comments: 0

M&A Mentor Graphics acquired the rest of Calypto. In 2011, Mentor sold Calypto their high-level synthesis solution – Catapult – in exchange for 51% of the company, but left it as a fully standalone entity. Calypto will now be merged into Mentor as a standalone business unit. Tools Synopsys released its HAPS-80 FPGA-based prototyping system. According to Synopsys, the system pro... » read more

Blog Review: Sept. 16
By Jesse Allen - 16 Sep, 2015 - Comments: 0

Ansys' Justin Nescott presents five top engineering articles for the week. Being an amateur photography buff, I start salivating at a 250 megapixel camera. Plus, origami and the art of structural engineering and a football-playing robot. Synopsys' Michael Posner provides some shocking information about the buildup of static electricity and the impact it can have on 28nm designs. Increasin... » read more

Appetite For Services Grows
By Ed Sperling - 11 Sep, 2015 - Comments: 0

Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more techniques, languages and methodologies that engineers need to learn to be productive in the finFET generation. The services business typically acts as a bridge between down and up cycles in the c... » read more

The Week In Review: Design/IoT
By Ed Sperling - 11 Sep, 2015 - Comments: 0

Tools Mentor Graphics rolled out a new version of its tool for transferring PCB designs into data for fabrication, assembly and test. The company also announced that its debug environment will support the UPF Low Power Successive Refinement Methodology. Deals Ansys and Cray are claiming the world's record for simulation by scaling 129,000 cores. That's about 4X the previous record.  Ansys... » read more

New Metrics For The Cloud
By Ed Sperling - 10 Sep, 2015 - Comments: 0

Data centers are beginning to adjust their definition of what makes one server better than another. Rather than comparing benchmarked performance of general-purpose servers, they are adding a new level of granularity based upon what kind of chips work best for certain operations or applications. Those decisions increasingly include everything from the level of redundancy in compute operations, ... » read more

Integration Or Segregation
By Brian Bailey - 10 Sep, 2015 - Comments: 0

In the Electronics Butterfly Effect story, the observation was made that the electronics industry has gone non-linear, no longer supported by incremental density and cost-reducing improvements that Moore’s Law promised with each new node. Those incremental changes, over several decades, have meant that design and architecture have followed a predictable path with very few new ideas coming in ... » read more

Deciphering Performance Analysis
By Ann Mutschler - 10 Sep, 2015 - Comments: 1

Simulation traditionally has been the go-to technology for improving system performance, but practices are evolving and maturing because engineering teams need to be able to simulate in multiple domains and at at multiple levels of abstraction. In addition, they need to tune the level of [getkc id="11" kc_name="simulation"] they are using to what types of models they have available, and what ki... » read more

FPGA’s Role Expands
By Ann Mutschler - 10 Sep, 2015 - Comments: 1

For more than a decade FPGA vendors argued that FPGAs would become a viable alternative to ASICs, adding programmability along with the same kind of advances in performance and power that ASICs saw at each new process node. While that never played out as they expected, FPGAs nonetheless have carved out a formidable position in the semiconductor market. Generally speaking, FPGAs today are us... » read more

Power Estimation: Early Warning System Or False Alarm?
By Brian Bailey - 10 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kulkarni, senior vice president and general m... » read more

Two Constraints-Based Techniques To Address Power-Related Challenges In SoC Design
By Christine Young - 10 Sep, 2015 - Comments: 0

Power scheduling, power integrity targets, voltage drop—these are just a few of the power-related challenges you’re no doubt managing in your SoC designs. There aren’t any easy answers, but there are some emerging—and promising—techniques. Two such techniques, according to University of Toronto Professor Farid Najm, are constraints generation and constraints-based verification. “... » read more

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