tag: Cadence

Analog’s Day Of Reckoning
By Brian Bailey - 16 Jun, 2015 - Comments: 0

The numbers being touted by the semiconductor industry for IoT edge devices are staggering. How they are going to be used, who will make them, or indeed who will make money from them are much less certain. The industry seems to be clear about the content of these devices. A small processor, some flash memory or possibly even some of the new memory technologies that are coming along, a radio ... » read more

IP Integration Challenges Increase
By Ed Sperling - 16 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

Mentor, Cadence Join Forces
By Ed Sperling - 15 Jun, 2015 - Comments: 0

Mentor Graphics and Cadence have agreed to create a single binary interface for their respective simulation and emulation platforms, allowing debug tools from one vendor to run on the other's platforms. The two have invited [getentity id="22035" e_name="Synopsys"] to join their initiative, as well. So far, there is no decision. The move proposes a single API for both [getentity id="22032"... » read more

Formal Low-Power Verification Of Power-Aware Designs
By Cadence - 15 Jun, 2015 - Comments: 0

Power reduction and management methods are now all pervasive in system- on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design th... » read more

The Week In Review: Design/IoT
By Jesse Allen - 12 Jun, 2015 - Comments: 0

Mergers & Acquisitions Synopsys announced Sunday it would acquire privately held formal verification provider Atrenta, for an undisclosed sum. That was followed quickly by Ansys' announcement that it would buy data analytics firm Gear Design Solutions. Tools IC Manage uncorked its big data predictive analytics tool Envision, which provides real-time design progress analytics to pre... » read more

DAC 2015: Day 4
By Brian Bailey - 11 Jun, 2015 - Comments: 0

Are you ready for the self-driving car? Threats come from other cars – not necessarily hitting you but hacking you. Day four of DAC started with a keynote panel moderated by John McElroy of Blue Sky Productions and panelists included Jeff Massimilla from General Motors and Craig Smith from Theia Labs/OpenGarages.org/IATC. "What would happen if cars started picking up viruses," asked Anne C... » read more

DAC 2015: Day 3
By Brian Bailey - 10 Jun, 2015 - Comments: 0

The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled "Crossing the Great Divide: How to Safely Navigate the move from 28nm to 16FF+." The panel was moderated by Brian Fuller and panelists included Jayanta Lahiri from ARM, Afshin Montaz from Broadcom, Scott McCormack from Freescale, Yan... » read more

Blog Review: June 10
By Jesse Allen - 10 Jun, 2015 - Comments: 0

The humble flatworm is leading limb regeneration research, a mystery company keeping quiet about its advancements towards fusion energy, and more in this week's top picks by Ansys' Bill Vandermark. How far should one go in the name of white hat hacking? Rambus' Aharon Etengoff provides a perspective on the ethical limits of an issue recently thrown into the spotlight How do you bring toge... » read more

Full Coverage Or Full Monty?
By Brian Bailey - 09 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

DAC 2015: Day One
By Brian Bailey - 08 Jun, 2015 - Comments: 0

It requires a certain dedication to attend technical DAC sessions on a Sunday morning, but full day workshops start before 9:00am for those dedicated to hearing about the latest work being conducted in academia and the research arm of industry. These are highly technical sessions that target academics and those serious about keeping a pulse on up and coming technologies. One such workshop wa... » read more

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