tag: Cadence

The Week In Review: Manufacturing
By Mark LaPedus - 05 Jun, 2015 - Comments: 1

In what was called a defensive measure by some, Intel has announced a definitive agreement to acquire Altera for $54 per share in an all-cash transaction valued at approximately $16.7 billion. Here’s what one analyst said about the deal. “We continue to believe Intel’s pursuit of Altera–at a significant premium–was based on a defensive position, rather than the purely accretive str... » read more

Asynchronous Design: Is It Time Yet?
By Barry Pangrle - 05 Jun, 2015 - Comments: 0

Non-mainstream technologies can offer advantages over more commonly used approaches, but usually at some additional cost (otherwise they’d probably be mainstream). The additional cost could be in design time, area, testability or whatever, and it might even be only a temporary disadvantage. If comparable time and energy were invested in the new technology, perhaps the additional costs would d... » read more

The Week In Review: Design/IoT
By Jesse Allen - 05 Jun, 2015 - Comments: 0

Tools Cadence unveiled Genus, their next-generation RTL synthesis and physical synthesis engine incorporating a multi-level massively parallel architecture and physically aware context-generation capability. Using it for their recent PowerVR GE7800 GPU, Imagination reported a 5X improvement in turnaround time versus the previous Cadence synthesis solution with no impact on power, performance... » read more

Blog Review: June 3
By Jesse Allen - 03 Jun, 2015 - Comments: 0

An emergency torch that lets you breathe while escaping a smoke-filled building; a car that shrinks to fit into parking spaces that aren't quite big enough: from extreme situations to everyday activities, Ansys' Justin Nescott features devices designed to make life easier and safer in his picks for week’s top five engineering articles. Check out the prosthetic foot that takes commands from se... » read more

Emulation for Power
By Ann Mutschler - 01 Jun, 2015 - Comments: 0

Solving power problems in today’s leading-edge SoCs requires not only the best architectural choices but advanced tools and techniques to determine the right path to take. This equates to a combination of hardware emulation and power analysis/optimization software tools. Design teams today must have real-life scenarios to accurately predict the power impact of their architectural decisions... » read more

M&A Season Now Officially Open
By Ed Sperling - 28 May, 2015 - Comments: 0

A year ago many people were making jokes quite openly about the IoT. It wasn't uncommon to hear quips about the Internet of Nothing, the Internet of Disconnected Things, the Internet of Cars, or some other variant that questioned just how connected everything would become. The tenor of the conversation has changed significantly in the past year. The jokes are fewer, the stakes are higher. An... » read more

What’s Different At 16/14nm?
By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Full Coverage Or Full Monty
By Brian Bailey - 28 May, 2015 - Comments: 1

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Toward Smarter Design Automation
By Frank Schirrmeister - 28 May, 2015 - Comments: 0

In less than two weeks, the EDA industry will convene for its biggest conference of the year, the Design Automation Conference, again in San Francisco. Last year, I “came clean” with a post called “Confessions Of An ESL-Aholic,” pointing out that beyond high-level synthesis, a significant shift towards a more abstract design description than RTL has not yet happened and that a lot of th... » read more

Automating Root-Cause Analysis To Reduce Time To Find Bugs by Up To 50%
By Cadence - 27 May, 2015 - Comments: 0

If you’re spending more than 50% of your verification effort in debug, you’re not alone. For many design, verification, and embedded software engineers as well as engineers verifying complex standard protocols, debug is the primary bottleneck in verification. Most debug today is completed using the traditional methodology of print statements paired with waveforms. Given that today’s desig... » read more

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