tag: Cadence

The Controversial Spec
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

More Efficient Things
By Qi Wang - 11 Jul, 2013 - Comments: 0

By Qi Wang There are many angles to consider when it comes to efficiency and the Internet of Things (IoT). At the architectural level, the IoT system consists of connected things, the networks and the cloud servers for massive data processing. Efficient data storage and servers means lower power consumption, which will result in millions of dollars in savings. For the connected things thems... » read more

Blog Review: July 10
By Ed Sperling - 10 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster rolls out part four of his epic functional verification study, this one on design and verification reuse. If you work in the verification world, pounce. Cadence’s Brian Fuller looks back over a quarter century of technology—and what the average salary of a hardware design engineer will be in a 15 years: $499,000. But what will a cup of coffee cost?... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest ... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 28 Jun, 2013 - Comments: 0

Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director of product market... » read more

Experts At The Table: SoC Prototyping
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, for the system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: How... » read more

New Reliability Issues Emerge
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

The New Verification Landscape
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

Memory Gets Smarter
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

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