tag: Cadence

When Worlds Collide: Saving Power In Communications Applications
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler The interplay of hardware and software is a given in every device that contains a semiconductor chip, but is typically felt more acutely in communications applications given the extremely close dependencies for everything power-related. Managing power in these situations just gets more challenging as consumers demand more and better applications on their tablets, smar... » read more

The Next Big Challenge
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Software is the next big target in the quest to make electronics more energy efficient, but it’s proving a far bigger challenge than most systems architects originally believed it would be. There are several very large big problems to deal with in software. Writing efficient code for small processors isn’t one of them. In fact, the proliferation of small processors across... » read more

Status Report: Power-Aware Design Flow
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler While the term “design flow” can be a moving target, there are some specific requirements for a low-power/power-aware tool flow. Looking at this from a high level, where is the industry today, and where is it headed? There are really two sides to power, which are almost like two sides of the same coin: power consumption and power integrity. And both of those ar... » read more

Rethinking Good Enough
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Power has been elevated from an afterthought to one of the top considerations and tradeoffs in SoC design, edging out performance and area in many cases and in some cases even cost and features. Tradeoffs in design always change, depending upon what the most pressing concern is among consumers at any time. For decades, performance was always the top of anyone’s list, follow... » read more

How Long Will 28nm Last?
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler As soon as a next generation semiconductor manufacturing process node is out, bets are taken on just how long the current advanced process node will last. The 28/20nm transition is no exception. There is certainly a benefit to moving from 40nm to 28nm. The  availability of high-k/metal gate technology offers quite a few advantages in terms of power reduction... » read more

Power Intent Formats: Reality Check
By Luke Lang - 12 Jan, 2012 - Comments: 2

By Luke Lang It is January once again. In addition to wishing everyone a Happy New Year, I would like to wish everyone a lower-power 2012. This month, I will continue with the CPF/UPF power format discussion and examine more complex power architectures. Also, the focus will be only on CPF 1.1 and UPF 1.0. These are what the current tools support. IEEE 1801 is up and coming, but there is n... » read more

Experts At The Table: Making Software More Energy-Efficient
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss software and power with Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Pete Hardee, marketing director at Cadence; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior vice president and general manager of Apache Design, and Bill Neifert, CTO of Carbon Design Systems. What follows are excerpts of that conversation. LPE: Softw... » read more

Making Software Better
By Ed Sperling - 11 Jan, 2012 - Comments: 0

Low-Power Engineering talks about what will make software more energy-efficient with Pete Hardee, marketing director at Cadence; Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior VP and General Manager of Apache Design, and Bill Neifert, CTO of Carbon Design. [youtube vid=Jxquj8K8_BA] » read more

Too Many Standards, But Still Not Enough
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ed Sperling The semiconductor industry has been one of the most prolific sectors in history when it comes to generating standards. Talk to any design engineer facing time-to-market pressures, new packaging approaches, and a mindboggling number of merchant IP, subsystems and interface requirements, and you’ll hear a compelling pitch for new standards. Talk to his or her boss and you’ll p... » read more

Model-Driven Design: Making Progress
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ann Steffora Mutschler Model-driven design is coming into its own, in part because the old way of using models at advanced nodes doesn’t always produce usable chips and in part because of the need for making tradeoffs at the earliest stages of the design process. The concept of developing models for IC design is hardly a new one, and it is being done today on a number of levels rangin... » read more

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