tag: Cadence

What To Expect In 2012
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ann Steffora Mutschler Looking at the biggest challenges for system-level design in 2012, model availability, IP integration and hardware/software co-design top everyone’s list. The integration of IP and enabling that from a system-level perspective is a significant challenge for the industry. Moreover, it will become even more significant as the market moves further down the Moore’s... » read more

After The Ball Drops
By Atrenta - 14 Dec, 2011 - Comments: 0

Growing up in New York City leaves lasting memories. The coming holiday season evokes some strong ones. The Christmas tree in Rockefeller Center is an example. Christmas always seemed to radiate in all directions from that huge tree perched above the ice skating rink behind Radio City Music Hall. And then there was the ball dropping on New Year’s Eve in Times Square. For the most part, New Yo... » read more

All I Want For Christmas … Is A Census Of Software Developers!
By Frank Schirrmeister - 14 Dec, 2011 - Comments: 0

By Frank SchirrmeisterThe year is almost over and in my homeland of Germany, kids are preparing to appease Santa Claus and Knecht Ruprecht (the guy who gives you a rod if you misbehaved during the year) with a Christmas rhyme. I remember that as a kid, I was at one point reciting from memory the second chapter from the book of Luke: “In those days Caesar Augustus issued a decree that a census... » read more

Power Intent Formats
By Luke Lang - 01 Dec, 2011 - Comments: 0

The October blog about CPF, UPF 1.0, and IEEE 1801 power domain definitions resulted in some reader feedback and suggestions. Several points are worthy of further discussion and clarification. Let me start with the toughest questions. What is my motivation behind the blog? Am I trying to make CPF look better than UPF/IEEE 1801? My preferred choice of power intent should not be a surprise ... » read more

Energy Vs. Power: Energy, Power Optimization Is A System-Level Challenge
By Ed Sperling - 01 Dec, 2011 - Comments: 0

By Ann Steffora Mutschler Power issues today, whether they are related to low power in a smart phone or highly efficient power for data center applications, are so pervasive that they touch the entire design team—and must be carefully prioritized at the system or architectural level. As discussed in Part 1 of this series, energy and power are different entities and must be understood dist... » read more

Playing The Voltage Game
By Ed Sperling - 01 Dec, 2011 - Comments: 0

y Ed Sperling Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages. The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing... » read more

Experts At The Table: Managing Power At Higher Levels Of Abstraction
By Ed Sperling - 18 Nov, 2011 - Comments: 0

Low-Power Engineering sat down to discuss the advantages of dealing with power at a high level with Mike Meyer, a Cadence fellow; Grant Martin, chief scientist at Tensilica; Vic Kulkarni, senior vice president and general manager at Apache Design; Shawn McCloud, vice president of marketing at Calypto; and Brett Cline, vice president of marketing at sales at Forte Design Systems. What follows ar... » read more

Make Vs. Buy
By Ed Sperling - 17 Nov, 2011 - Comments: 0

By Ann Steffora Mutschler The confounding ‘make versus buy’ decision is understandably muddled by design complexity. Millions of gates, thousands of blocks, dozens of cores, plus software, packaging, and worries about physical effects don’t make this decision any easier. In some cases the process can be simplified by mandating that anything that doesn’t add differentiation really is... » read more

Build It Faster
By Ed Sperling - 17 Nov, 2011 - Comments: 0

By Ed Sperling Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking. Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, par... » read more

Mapping Out The Value Of TLM Modeling
By Frank Schirrmeister - 16 Nov, 2011 - Comments: 1

I have written about the value of system-level design and moving up to next level of abstraction numerous times. This fall one of the most interesting steps of progress towards effective system-level design and emphasis on the importance of embedded software has been made by the two big FPGA vendors Altera and Xilinx. Both vendors have announced devices combining programmable logic of up to sev... » read more

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