tag: Cadence

Experts At The Table: Managing Power At Higher Levels Of Abstraction
By Ed Sperling - 11 Nov, 2011 - Comments: 0

Low-Power Engineering sat down to discuss the advantages of dealing with power at a high level with Mike Meyer, a Cadence fellow; Grant Martin, chief scientist at Tensilica; Vic Kulkarni, senior vice president and general manager at Apache Design; Shawn McCloud, vice president of marketing at Calypto; and Brett Cline, vice president of marketing at sales at Forte Design Systems. What follows ar... » read more

CMP, ST et al offer 28nm FD-SOI for prototyping, research
By Various Writers - 06 Nov, 2011 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What would a port to 28nm FD-SOI do for your design?  A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out.  Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact model... » read more

Five Important Changes That Will Affect Power
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Ed Sperling So far most of the energy savings in SoCs have been achieved using two main approaches—turning off most of the chip most of the time, and changing the materials used to insulate against current leakage. Over the next few years, changes to designs will be more radical, encompass more pieces of a bigger system, and they will be orders of magnitude more effective. From a marke... » read more

Energy Vs. Power
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Ann Steffora Mutschler In the quest to optimize an SoC for both power and energy efficiency many variables come into play. Target application, use cases, processor choice and amount of memory among other specifications all figure into the optimization equation. As discussed in Part 1 of this series, energy and power are different entities and must be understood distinctly from each other... » read more

Power Intent Formats: Isolation
By Luke Lang - 03 Nov, 2011 - Comments: 0

By Luke Lang Last month, I discussed power domain for all three power formats: CPF, UPF 1.0, and IEEE 1801. I mentioned isolation but mainly used it to explain power domain. This month’s blog will address isolation in detail. First, isolation cells are required at off-to-on domain crossings. When a domain is shut off, all of its output nets become undriven. If these floating nets drive direct... » read more

Experts At The Table: Managing Power At Higher Levels Of Abstraction
By Ed Sperling - 03 Nov, 2011 - Comments: 0

Low-Power Engineering sat down to discuss the advantages of dealing with power at a high level with Mike Meyer, a Cadence fellow; Grant Martin, chief scientist at Tensilica; Vic Kulkarni, senior vice president and general manager at Apache Design; Shawn McCloud, vice president of marketing at Calypto; and Brett Cline, vice president of marketing at sales at Forte Design Systems. What follows ar... » read more

Using High-Level Synthesis To Manage Power
By Ed Sperling - 02 Nov, 2011 - Comments: 0

Low-Power Engineering talks with Apache Design's Vic Kulkarni, Tensilica's Grant Martin, Cadence's Mike Meyer, Calypto's Shawn McCloud and Forte Design's Brett Cline about the need for a higher level of abstraction to optimize power in ICs. [youtube vid=gpWacAhMYgo] » read more

Experts At The Table: Mobile Design Challenges
By Ed Sperling - 21 Oct, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation. ... » read more

The Next SoCs
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ed Sperling The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips. System-Level Design asked executives from across the SoC ecosystem what will change, what’s d... » read more

Derivative Designs Demand Discipline
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler By and large most designs today are derivatives, meaning they don’t start from a blank slate. And while that gives engineering teams a starting point, it also can make adding new IP blocks or changes to the design problematic, with the potential for increased routing and timing issues along with considerable pain to back-end engineers and delays in chip schedules. ... » read more

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