tag: Cadence

Virtual LP
By Luke Lang - 09 Feb, 2012 - Comments: 0

By Luke Lang Several months ago, I introduced the concept of virtual domain in association with hierarchical CPF. It is a relatively simple concept with a concise definition. It is powerful and flexible in supporting large designs with complex power architecture and hierarchical power intent. However, to the UPF coders, virtual domain is sometimes a mystery. I hope this blog will clear up any ... » read more

A Brief History Of Power Formats
By Barry Pangrle - 09 Feb, 2012 - Comments: 0

Barry Pangrle A lot has happened in the industry in the way of power format standards over the past seven years. I’m going to attempt to hit on some of the highlights over that time period, especially with regards to the “Big 3” EDA vendors to hopefully put it all into better context for our readers. Early on, circa 2005, Mentor Graphics was working on a power format referred to as th... » read more

Experts At The Table: Making Software More Energy-Efficient
By Ed Sperling - 27 Jan, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss software and power with Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Pete Hardee, marketing director at Cadence; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior vice president and general manager of Apache Design, and Bill Neifert, CTO of Carbon Design Systems. What follows are excerpts of that conversation. LPE: How m... » read more

Reverse Engineering
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ed Sperling Fabs and foundries frequently have been the savior of flawed designs, fixing problems such as power and performance, identifying design issues and often developing solutions to those problems. Over the next couple of process nodes, and in stacked die that will span multiple processes, there will be far fewer saves coming from the back end. Double and triple patterning, stress... » read more

Model Report Card
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ann Steffora Mutschler From its perspective as a leader implementing system level design methodology, STMicroelectronics is uniquely positioned to discuss issues and challenges related to the use of models in a variety of use cases. System-Level Design had the opportunity recently to discuss challenges in the modeling space with Jean-Marc Chateau, director of ST’s SPT (System Platforms a... » read more

Will It Work?
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ed Sperling Estimates of how much time it takes to verify a complex SoC are still hovering around 70% of the total non-recurring engineering costs, but with more unknowns and more things to verify it’s becoming harder to keep that number from growing. Verification has always been described as an unbounded problem. You can always verify more, and just knowing when to call it quits is so... » read more

Roundtable: What’s Changing In System-Level Design
By Ed Sperling - 26 Jan, 2012 - Comments: 0

System-Level Design talks about what's changing and what's needed with Juan Rey of Mentor Graphics: Yervant Zorian of Synopsys; Michael McNamara of Cadence; Prasad Subramaniam of eSilicon; and Ravi Varadarajan of Atrenta. [youtube vid=8siiKBKD0-k] » read more

Will It Really Work?
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ed Sperling Estimates of how much time it takes to verify a complex SoC are still hovering around 70% of the total non-recurring engineering costs, but with more unknowns and more things to verify it’s becoming harder to keep that number from growing. Verification has always been described as an unbounded problem. You can always verify more, and just knowing when to call it quits is so... » read more

The Art Of Double-Indirect Sales And Product Marketing
By Frank Schirrmeister - 24 Jan, 2012 - Comments: 0

By Frank Schirrmeister The interaction between software and hardware development has been much discussed, with early software enablement being at the forefront of what system-level design in EDA tries to enable. The main reason why these discussions are so attractive to EDA – in my mind – is the impression that the number of software developers is significantly higher than that of hardware... » read more

Experts At The Table: Making Software More Energy-Efficient
By Ed Sperling - 20 Jan, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss software and power with Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Pete Hardee, marketing director at Cadence; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior vice president and general manager of Apache Design, and Bill Neifert, CTO of Carbon Design Systems. What follows are excerpts of that conversation. LPE: How d... » read more

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