tag: Cadence

Experts At The Table: IP
By Ed Sperling - 08 Mar, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion. LPE: Where ... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Pathfinding For Power And Heat
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling There are many ways to measure power and heat in an IC, and each one of them adds tremendous value to a design. But there are still holes, and those holes are just beginning to get filled. Power and heat have emerged as two of the most persistent problems in advanced designs, and there is no single or simple way to tackle either of them. Nevertheless, there is at least progre... » read more

Derivative ICs: A Look At The Options
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler With the cost of designing and producing even moderately advanced SoCs skyrocketing, semiconductor companies and systems houses must find ways to defray the cost across a larger number of end uses than ever. As such many companies have adopted a platform-based derivative design approach, with that the platform serving as the first SoC design of a new family. That s... » read more

Market Catches Up With Verification IP
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling Ever since verification IP was introduced it was seen as something that should be given away with purchased IP. The result was limited investment by IP vendors, frustration on the part of IP customers, and a market opportunity that nearly fizzled before it even began. But as the amount of commercially developed IP content continues to grow in ICs, the potential interactions ... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 22 Feb, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wha... » read more

Roundtable: ESL Grows As Processes Shrink
By Ed Sperling - 22 Feb, 2012 - Comments: 0

System-Level Design talks with Steve Bailey of Mentor Graphics, Michael (Mac) McNamara of Cadence Design Systems, Ghislain Kaiser of DOCEA Power and Shawn McCloud of Calypto about what will propel growth in the system-level design tools marketplace. [youtube vid=yBhLLN40mSE] » read more

Are Hardware Developers From Mars And Software Developers From Jupiter?
By Frank Schirrmeister - 21 Feb, 2012 - Comments: 0

By Frank Schirrmeister In a recent discussion fellow Blogger Kurt Shuler, when talking about hardware and software designers, said something along the lines “Given languages like Verilog, both hardware and software developers really do software, for hardware designers the software is just getting fixed much sooner.” I intuitively agreed with him, but his comment inspired this post in which... » read more

Margin Of Error
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ed Sperling Adding extra circuits and silicon area to a chip has always been frowned upon by chipmakers. Extra silicon means extra money, and for most chips the least expensive is always the better choice. But at advanced process nodes, margin also can slow performance, increase power consumption, and make it harder to achieve timing closure. The obvious solution is to reduce margin thro... » read more

Step Away From the Spreadsheet
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler Engineers today spend more than a quarter of their time trying to meet power specifications. A survey of more than 700 engineers by Calypto illustrates just how important and time-consuming power management is today for engineering teams. As consumer devices grow ever more complex, the need to deal with, analyze and optimize power at not just the RTL but at the sys... » read more

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