tag: Cadence

Verifying Low-Power Designs
By Ed Sperling - 14 Jan, 2010 - Comments: 0

By Ed Sperling Power islands and multiple voltages used to be reserved for cell phone and process companies, but as more companies move to 65nm and 45nm process nodes these approaches to saving power—particularly in chips with multiple cores—are becoming mainstream. The problem isn’t in the architecture of the chips, although that certainly brings its own set of challenges. More and m... » read more

Combining Power And Synthesis
By Ann Mutschler - 14 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the pro... » read more

Slow Start To Software-As-A-Service
By Pallab Chatterjee - 17 Dec, 2009 - Comments: 0

By Pallab Chatterjee Can software as a service (SaaS) really work in the SoC design tools world? While many of the large EDA vendors continue to experiment with it, the future of this model isn’t especially promising. This is contrary to the overall trend among big software makers, which even in the large enterprise applications space are finding success with SaaS and the related cl... » read more

Making DFM Work Better
By Ann Mutschler - 17 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase. There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital si... » read more

5 Reasons For Change
By Ed Sperling - 04 Dec, 2009 - Comments: 0

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their r... » read more

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

Power Trip Advisor
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Geoffrey James There’s never been a greater demand for power-efficient silicon. As consumer electronic devices get smaller, with increased functionality, battery power becomes a premium resource. At the same time, “Green IT” is a major corporate trend, and the best way to be environmentally sensitive (while saving on energy costs) is to buy technology that ekes the maximum computing o... » read more

Considerations For Choosing The Right Low-Power Tools
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

Verification As A Deterrent?
By Ed Sperling - 24 Sep, 2009 - Comments: 0

By Ed Sperling Verification is becoming more than a bottleneck in semiconductor design. It’s actually deterring companies from adopting the latest techniques for saving power or building certain features into chips. The problem is one of complexity, and it’s getting worse at every node. While the tools exist to do complex designs, there are the classic tradeoffs of area, power and per... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 04 Sep, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy