tag: Cadence

Balancing Quality, Cost And Locale
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler As more features are packed into a single SoC there are simply more time-critical decisions to make. Instead of holding up one chip of a six-chip chipset, a delay or error on one chip can stop the whole parade. That explains why one of the most vibrant parts of the business at big EDA companies these days is standard IP, and why most of the other commercial IP make... » read more

Unified Design Flows Require New Skill Sets
By Ed Sperling - 27 May, 2010 - Comments: 0

By Pallab Chatterjee With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools. These new tools were created to address the need for simultaneous Multi-Corner M... » read more

Same Industry, Different Shape
By Ed Sperling - 14 May, 2010 - Comments: 0

As the design industry plunges into DAC this year, it’s beginning to look like a completely different industry. It’s not the players themselves. There are still the Big Three EDA vendors, IP vendors and lots of startups. And it’s all still geared toward making chips. But the center of gravity has shifted from what was almost exclusively place and route and synthesis out to the edges of... » read more

A Shock To The System
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them. What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good... » read more

Killer Bugs
By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Ed Sperling Hardware and software bugs are all around us. When an application suddenly dies or a smart phone freezes because of the unanticipated interaction between hardware and software blocks in a system on chip, most users aren’t even the least bit fazed. They usually just re-boot and forget about it. Bugs caused by power are an entirely different matter, however. For one thing, ... » read more

Emulation 2010
By Ann Mutschler - 25 Mar, 2010 - Comments: 0

By Ann Steffora Mutschler In an industry that was once fraught with patent infringement lawsuits, hostile takeovers and other exciting corporate warfare, the hardware-assisted emulation market has quieted down considerably. That doesn’t mean it has lost its luster, though. It still plays an integral, if not ever-increasing and expanding, role in the verification efforts of most semiconductor... » read more

Slow Adoption for ESL
By Brian Fuller - 25 Mar, 2010 - Comments: 0

By Brian Fuller It’s been more than a decade since electronic system level (ESL) abstraction started to gain traction in EDA. It’s been more than a few years since the industry began to plan for the day when the benefits of embracing C-language approaches to design description and validation would find designers churning out massively complex and profitable designs while sitting in lawn ch... » read more

Stop Texting Me
By Ed Sperling - 25 Feb, 2010 - Comments: 0

By Brian Fuller It was a simple request for a story: “You play around with this social-media stuff: Is it having an impact within engineering organizations?” My first thought was “social” and “engineer” should not be in the same sentence. Someone recently told me a story about trying—through Twitter no less—to set up a face-to-face meeting with an engineer at a live event.... » read more

Should Sign-Off And Implementation Be Separate Tools?
By Ann Mutschler - 28 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler In the last stages of design, how data is readied for manufacturing used to be relatively straightforward. Point tools were used to implement the design via a place and route tool then the design was “signed off” with physical verification software. Sign-off is the gate the design goes through before it can go into manufacturing. The design must meet the qua... » read more

Journey To The Center Of The Ecosystem
By Ed Sperling - 14 Jan, 2010 - Comments: 0

From the outside it looks like business as usual, but the race for board seats on the GSA has become particularly competitive this year. GSA originally was created as an organization for fabless companies, but you wouldn’t know that looking at its membership roster. It has evolved into a who’s who of the entire semiconductor supply chain, including everyone from foundries like TSMC and... » read more

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