tag: Cadence

Getting Low-Power IP Integration Right
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler When it comes to integrating multivendor IP, power concerns dominate the challenges that engineers face. To get it right however, there are definitely questions that should be asked when considering which IP to use, along with techniques to manage power complexity. When choosing IP, the following points should be considered: How mature is the IP being sold? Has... » read more

The Power Of IP
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As the number of design starts goes down the corresponding complexity of SoCs has gone up—and continues to grow. Everyone is looking at the value they can bring to the table as increasing proportions of SoCs are either reused from pre-existing IP within the company designing the chip or brought in from outside. Because is economically impractical to start an SoC... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 08 Jul, 2010 - Comments: 0

Low-Power Engineering sat down to discuss a broad swath of power issues with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that conversa... » read more

End User Report: EDA Industry Realignment
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, ... » read more

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

The Future Of IP
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

The Road To DAC: One On One With Lip-Bu Tan
By Ed Sperling - 04 Jun, 2010 - Comments: 0

A look at what's driving Cadence's new EDA 360 strategy, the problem areas in EDA and why the company decided to buy Denali. [youtube vid=zreEWGsCe5A] » read more

The Great Divide
By Ed Sperling - 27 May, 2010 - Comments: 0

By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

TLM 2.0: Necessary for Co-Simulation
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

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