tag: Cadence

Defining Power Intent
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Designing power-sensitive SoCs has never been more challenging given the tremendous demand for power efficiency in applications ranging from smart phones to servers inside data centers. That makes describing the power control architecture of a chip through power intent essential. Specifically, explained Will Ruby, senior director of product engineering and applicat... » read more

Rethinking Models
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ed Sperling The move to future process nodes will require more than just new materials, better layouts and higher levels of abstraction. It also will require a fundamental re-thinking of how high-level architectural models are created and what’s included in them. While the Transaction-Level Modeling (TLM) 2.0 standard has provided significant improvements for everything from layout to ... » read more

iPhone Has The Power Blues
By Ann Mutschler - 12 Aug, 2010 - Comments: 0

Why do some apps on the iPhone seem to draw more on the battery than others? Is it a matter of power-aware software applications, or is it a hardware issue? Maybe it is a combination of both. I suspect it is due to the intricacies of hardware/software design and verification. I’ve been mulling this over while researching my two articles for this month’s issue of Low-Power Engineering... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 23 Jul, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpt... » read more

Why Open Source Matters
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler A huge effort has been under way to create virtual prototypes that allow true hardware/software co-design, but there are still a number of pieces missing. One significant missing element is a full library of IP models to guide the process, and the solution could come from an unlikely place—open source developers. Today, ‘open source’ IP generally seems to be ... » read more

ESL Requires New Approaches To Design And Verification
By Ann Mutschler - 22 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As more data gets front loaded into SoC architectures today, understanding verification challenges as well as communication between the front and back end has never been more critical. “All of this is getting more complicated,” said John Ford, director of marketing at ARM. “There was a time when an ARM processor core was all that was on a chip. Now there’s ... » read more

‘Good’ Vs. ‘Good Enough’
By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Ed Sperling The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who’s actually making that decision—as the amount of software being developed by hardware companies continues to grow. At the root of this shift are two very different concepts about what constitutes a market-ready product. For SoC engineers, fixing bugs after a chip has... » read more

What EDA360 Isn’t
By Atrenta - 22 Jul, 2010 - Comments: 0

By Mike Gianfagna The EDA360 White Paper that Cadence Design Systems published a few months back certainly has everyone talking. It’s well written. The messages are compelling. The content has a viral quality. The printed collateral is visually appealing. The microsite is engaging. Most of us only wish we had the marketing budget to do this kind of stuff. A healthy marketing budget is a n... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 16 Jul, 2010 - Comments: 0

Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that convers... » read more

Why Low-Power Analog Solutions Are Lacking
By Luke Lang - 08 Jul, 2010 - Comments: 0

By Luke Lang The need for low-power design has been well documented. The demand for low-power design solutions is at an all-time high. Just take a quick glance through the 2010 Design Automation Conference advanced program, and you’ll see that the word “low-power” appears repeatedly. These are exciting times for anyone associated with low-power design. Recent developments in low-power... » read more

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