tag: Cadence

Experts At The Table: Timing Constraints
By Ed Sperling - 15 Oct, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. Wha... » read more

Power Intent Files Drive Low Power Adoption
By Luke Lang - 07 Oct, 2010 - Comments: 0

By Luke Lang “The adoption of EDA tools is actually a very slow process.” This quote by Wally Rhines of Mentor Graphics was highlighted in a red box in the June 2010 issue of EDA Tech Forum. I don’t think most of us would argue with that statement. But there are certainly exceptions to that rule, and low-power design with a power-intent file is one such exception. The concept of a pow... » read more

Making Too Much Noise
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ed Sperling For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change. Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signal... » read more

Experts At The Table: Timing Constraints
By Ed Sperling - 07 Oct, 2010 - Comments: 0

Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. What follows are ex... » read more

Software Drives Design Requirements
By Ed Sperling - 23 Sep, 2010 - Comments: 0

By Ann Steffora Mutschler As product design evolves to contain more and more software, that software—including the applications that run on the device—is now starting to drive design and process requirements. This change is causing ripples throughout the semiconductor industry, driving evolutionary thinking about where to go next. OEMs have taken notice of a new dynamic and want to capt... » read more

Estimating Power From Mobile Device Apps
By Ann Mutschler - 09 Sep, 2010 - Comments: 0

By Ann Steffora Mutschler How do software application developers – even the ones sitting at home on their living room sofas with laptops – measure the power consumption of their application on the target device? This is a big problem today (something that is painfully obvious to owners of iPhones or Blackberries), and it will only get bigger. Software engineers may think it is not their... » read more

Burn, Baby, Burn
By Ann Mutschler - 09 Sep, 2010 - Comments: 0

Obviously, software burns power on mobile devices, but exactly how? I found out recently, thanks to Pete Hardee, director of solutions marketing at Cadence Design Systems. Essentially, Hardee said, there are four ways that software burns power, following in order from most to least. First, depending on the mode, various peripherals are on and off and the big one for a smartphone is the LC... » read more

What’s Next After DRAM?
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By Pallab Chatterjee At the most recent Denali Memcon, there was a panel discussion and debate about the future of DRAM and possible successor technologies. The discussion was moderated by Cadence’s Steve Leibson and featured Bob Merritt of Convergent Semiconductor, Barry Hoberman of Crocus, Ed Doller of Micron and Marc Greenberg of Denali/Cadence. The topic of the discuss was based on t... » read more

The Growing Software Challenge: From Stacks To SMP
By Ann Mutschler - 26 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications. With millions of different embedded products, all with different sets of software, it comes down to pr... » read more

Structural Verification Finds Mixed-Signal LP Errors
By Luke Lang - 12 Aug, 2010 - Comments: 0

By Luke Lang In the last blog, I gave some reasons why there is no low power (LP) analog/mixed-signal solution. However, this does not mean there is no effort in this area. Toward the end of 2009 and early 2010, I worked with a customer to establish a LP analog/mixed-signal structural verification flow. This flow was proven to be extremely helpful. It caught several LP bugs that were not found... » read more

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