tag: Cadence

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 28 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 20 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

Who’s In Control Now?
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

ESL: Reality, Or A Pigment Of Your Fig Neuton?
By Various Writers - 31 Jul, 2009 - Comments: 0

By Clive "Max" Maxfield One of the questions I am often asked is: "Who's really using ESL tools such as modeling and are there any hiccups in the flow?" Another common question is: "What actually is ESL?" Perhaps we should address the latter question first. To some folks, ESL (electronic system level) means designing at a very high level of abstraction prior to making any hardware-softwar... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

Making Quality A Top Priority in Next-Generation Designs
By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

Formal Verification 101
By Various Writers - 27 May, 2009 - Comments: 0

By Clive "Max" Maxfield The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all "worked." The idea that the statements in the modeling language acted in a concurrent manner just seemed to make sense. By comparison, trying to wrap my brain around formal verification has always mad... » read more

Where SaaS Works Best
By Ed Sperling - 27 May, 2009 - Comments: 0

By Ed Sperling Some of the largest corporations in the world use software-as-a-service, or SaaS to run their enterprise applications, trusting day-to-day operations to companies like Salesforce.com, Oracle, Microsoft and even Google. But good luck finding any leading-edge chip vendors utilizing the SaaS model for their designs. While Cadence has been successful with some of its low-end to... » read more

Taming The Multicore Beast
By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Multicore chips are here to stay. Now what? That question is echoing up and down the ranks of tools vendors, design engineers, software developers and even among people who measure the performance and efficiency of semiconductors. There is now a Multicore Expo and a Multicore Association that includes a who’s who of electronics. And there are lots of working groups developing... » read more

Thinking Digital To Design Analog, And Vice Versa
By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome. Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with is... » read more

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