Backside Power Delivery as a Scaling Knob for Future Systems

By Coventor - 14 Aug, 2019 - Comments: 0

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO explorat... » read more

Manufacturing Bits: July 30

By Mark LaPedus - 30 Jul, 2019 - Comments: 0

Scanning nanopore microscopes ETH Zurich has developed a new microscopy technique that can detect and analyze signals between individual cells in living organisms. The technology, called a force-controlled scanning nanopore microscope, is a new way to look at the behavior of individual cells. So far, researchers have tested the technology on rat brain tissue. It could one day be used to pro... » read more

Manufacturing Bits: May 12

By Mark LaPedus - 12 May, 2015 - Comments: 0

Photonic thermometers The National Institute of Standards and Technology (NIST) has developed a new class of photonic thermometers. These chip-based thermometers measure temperature using light. They are resistant to electromagnetic interference and are self-calibrating. In the future, photonic thermometers could be buried into walls or sent into space. They could be used for chemical, pres... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: cell

Backside Power Delivery as a Scaling Knob for Future Systems

Manufacturing Bits: July 30

Manufacturing Bits: May 12