tag: DO-254

What Can Go Wrong In Automotive
By Ed Sperling - 06 Oct, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

The Real Differences Between HW And SW
By Brian Bailey - 03 Oct, 2016 - Comments: 0

How many times have we heard people say that hardware and software do not speak the same language? The two often have different terms for essentially the same thing. What hardware calls constrained random test is what software people call fuzzing. Another one recently caught my eye in a conversation with Jama Software, a Portland software company that has made a name for itself in requiremen... » read more

The Hardest Part Of DO-254 Is…
By Louie De Luna - 26 May, 2016 - Comments: 0

The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification. We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees from major aerospace companies including Curtiss Wright, Rolls Royce, Sierra Nevada Corporation, Thales and Woodward. It’s always a pleas... » read more

Planes, Cars, And Lagging Standards
By Ed Sperling - 28 Mar, 2016 - Comments: 0

Automotive and aerospace standards are struggling to adapt to pervasive connectivity, increased functionality, and new packaging approaches and architectures, leaving chipmakers and systems vendors unsure about what needs to be included in future designs. Each of these markets has a reputation for being lumbering and unresponsive, in part because they deal with safety-critical issues and i... » read more

Q&A With FAA DO-254
By Aldec - 23 Mar, 2016 - Comments: 0

Aldec together with FAA DER Randall Fulton conducted a webinar to provide clarifications on some of the most commonly misunderstood objectives and aspects of DO-254. The following is the list of questions that were submitted to Aldec for the webinar. All questions are related to applying DO-254 to FPGAs and PLDs. The answers from Randall Fulton are provided correspondingly. To read more, c... » read more

Managing Validation And Verification Abstract Activities For DO-254
By Aldec - 24 Feb, 2016 - Comments: 0

This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & ... » read more

Finding CDC Issues Before They Find You
By Aldec - 27 Jan, 2016 - Comments: 0

Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated. To read more, cl... » read more

The Problem With CDCs
By Louie De Luna - 24 Nov, 2015 - Comments: 0

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

Developing High-Reliability FPGAs For DO-254
By Louie De Luna - 27 Aug, 2015 - Comments: 0

You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in Hawaii. You can manually write down your memory mapping accurately while under oath. You can pinpoint all CDC paths and emulate metastability in your... » read more

Blog Review: Aug. 26
By Jesse Allen - 26 Aug, 2015 - Comments: 0

Synopsys' Marc Greenberg attended IDF and learned more about the newly announced Intel/Micron 3D XPoint memory technology named Optane including initial ship dates and some implementation details. In concluding his analysis of the 2014 Functional Verification Study, Mentor's Harry Foster reveals an unexpected finding about design size and respins. How do you keep your power grid from bein... » read more

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