tag: EDA

FD-SOI Vs. FinFETs
By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Tech Talk: Mobile Security (Part 2)
By Ed Sperling - 15 Apr, 2015 - Comments: 0

Simon Blake Wilson of Rambus' Cryptography Research Division talks about where security needs to fit into the design flow and where the biggest risks are. To view part one of this video, click here. [youtube vid=_nnniakpP3M] » read more

EDA Sets New Record
By Ed Sperling - 13 Apr, 2015 - Comments: 0

EDA revenue grew 11.9% in Q4 2014 to $2.1 billion, a new record for the industry, propelled by strong growth in both IP and physical design. On a sequential basis, that represented a 15.1% increase, while on a year-over-year basis it was 11.9%. The four-quarter moving average, which takes into account quarterly aberrations, showed a 7.3% increase. "The semiconductor industry had a strong ... » read more

Ecosystem Changes
By Ed Sperling - 07 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

First Time Success and Cost Control
By Brian Bailey - 01 Apr, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Blog Review: April 1
By Jesse Allen - 01 Apr, 2015 - Comments: 0

A Russian plan to build a massive cargo plane to deliver tanks at supersonic speed—A roll of tape coated in squid proteins provides perfect camouflage—A yacht made of volcanic fibers battling the world's roughest seas: Ansys' Justin Nescott finds everything for a James Bond movie in this week's top tech articles. Writing for Synopsys, Broadcom's Hari Balisetty looks at reusable sequences... » read more

Design By Architect Or Committee?
By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

Chip-Package-Board Optimization: The Future Of Integrated Co-Design
By John Park - 26 Mar, 2015 - Comments: 0

Multi-die and three-dimensional packages have made breakout and routing of extremely high-pin-count devices on PCBs very difficult. Keeping track of all the signals and pins is also a task that has just about outgrown current methods. Many companies simply use a spreadsheet for tracking signals. With no central database or accurate device modeling and rule-based optimization, design intent is o... » read more

Tech Talk: IoT Design Changes
By Ed Sperling - 25 Mar, 2015 - Comments: 0

eSilicon's Lisa Minwell talks with Semiconductor Engineering about what's needed to push Internet of Things designs down to the microwatt range, and how to bridge the gap between what's available today and what's needed for the future. [youtube vid= bk3BgtJnFpg] » read more

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