Experts At The Table: Yield Issues


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Experts At The Table: Yield Issues


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

Qualcomm Shies Away From High-k At 28nm


By David Lammers Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28 nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy, which because of Qualcomm’s size will have a major impact on the foundry business, at the 2010 International Electron Devices Meeting (IEDM) held in ... » read more

Power Optimization Below 28nm


By Pallab Chatterjee Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction. The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also h... » read more

Building Up In 3D


By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

The Future Of 3D Stacking


By Ed Sperling Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed. The first wave, which is expected to start showing up late next year, will likely come from a handful of t... » read more

What’s In The Package?


By Ann Steffora Mutschler The growing market for smart mobile devices and high-performance processors requiring more than 2GHz of processing power is driving IP providers to do even more work to prepare their IP offerings for customers. This theme was reflected at last week’s GlobalFoundries Global Technology Conference when the company’s senior VP of technology and R&D Gregg Bartle... » read more

The Shape Of Things To Come


By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

Betting On 3D


The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

The Growing Problem With Parasitic Extraction


By Ed Sperling Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node. There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. ... » read more

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