Bespoke Silicon Redefines Custom ASICs

By Ann Mutschler - 28 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

Hyperconnectivity, Hyperscale Computing, And Moving Edges

By Frank Schirrmeister - 27 May, 2021 - Comments: 0

As described in “The Four Pillars of Hyperscale Computing” last year, the four core components that development teams consider for data centers are computing, storage, memory, and networking. Over the previous decade, requirements for programmability have fundamentally changed data centers. Just over a decade ago, in 2010, virtual machines would compute user workloads on CPU-centric archite... » read more

Hyperconnectivity And The Path To 6G

By Frank Schirrmeister - 22 Apr, 2021 - Comments: 0

Some may view the recent uptick in the news about next-generation wireless networking, specifically 6G, with some healthy skepticism as 5G is “just rolling out.” But when looking at the timelines, it becomes clear why 6G is critical and is also excellent news for electronics, and by extension, the design of semiconductors and systems. The same key elements that transformed the data center t... » read more

The Four Pillars Of Hyperscale Computing

By Frank Schirrmeister - 27 Aug, 2020 - Comments: 0

In his keynote at CadenceLIVE Americas 2020, Facebook’s Vijay Rao, director, Technology and Strategy, described the four core elements the team considers when designing their data centers—compute, storage, memory, and networking. Wait a minute. Facebook? How did we get here? Wasn’t EDA supposed to be focused on chip design? As indicated in a previous blog, electronic value chains are defi... » read more

Huge Performance Gains Ahead

By Ed Sperling - 30 Aug, 2018 - Comments: 0

Rambus Chief Scientist Craig Hampel talks about what will drive the next big performance gains after Moore’s Law, from the data center to the edge. https://youtu.be/ItHCsei7YTc » read more

Executive Insight: Lip-Bu Tan

By Ed Sperling - 06 Sep, 2017 - Comments: 2

Semiconductor Engineering sat down with Lip-Bu Tan, president and CEO of [getentity id="22032" e_name="Cadence"], to discuss disruptions and changes in the semiconductor industry, from machine learning and advance packaging to tools and business. What follows are excerpts of that conversation. SE: What do you see as the next big thing? Tan: Unlike mobility or cell phones, or PCs before th... » read more

Conflicting Goals In Data Centers

By Gale Morrison - 06 Apr, 2017 - Comments: 0

Two conflicting goals are emerging inside of data centers—speed at any cost, and the ability to extend hardware well beyond its expected lifetime to amortize that cost. Layered across both of those are concerns about how to move data back and forth more efficiently, how to secure it, and how to best integrate different generations of technology. But these widely different goals have create... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: hyperscale computing

Bespoke Silicon Redefines Custom ASICs

Hyperconnectivity, Hyperscale Computing, And Moving Edges

Hyperconnectivity And The Path To 6G

The Four Pillars Of Hyperscale Computing

Huge Performance Gains Ahead

Executive Insight: Lip-Bu Tan

Conflicting Goals In Data Centers

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