PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2


As PCI Express (PCIe) evolves through Gen4, Gen5, and now Gen6, the complexity of high-speed design continues to grow. Signal and power integrity, equalization, clocking, and compliance — every layer of the PCB must be optimized for speed and reliability. The PCIe Design Guide – Q&A (Part 2) expands on the first volume with a deep dive into simulation, validation, and compliance, a... » read more

Combining SPICE With IBIS-AMI: Solving Advanced Signal Integrity Verification Challenges With Solido SPICE


This paper explores current technology trends in high-speed links, including high-speed memory and SerDes applications, highlighting the critical roles of combined SPICE-level and IBIS-AMI modeling for accurate verification. Verifying high-speed links with IBIS-AMI during the circuit design phase presents significant complexity due to the combined effects of equalization schemes, channel S-para... » read more