tag: in-chip monitoring

Secure Silicon Lifecycle Management Architecture For Functional Safety
By Lee Harrison - 08 Oct, 2020 - Comments: 0

The rapid growth of electronics for automotive applications fueled by advanced ADAS systems pose new challenges for complex SoC design and Silicon Lifecycle Management (SLM) in the supply chain as well as in-field monitoring and management of the population of chips. In these modern complex devices, ensuring the correct and safe operation requires not only functional safety to check for reli... » read more

Ins And Outs Of In-Circuit Monitoring
By Ed Sperling - 21 Jul, 2020 - Comments: 2

At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

‘Speak No Evil’ And SoC Problems
By Tim Penhale-Jones - 09 Jul, 2020 - Comments: 0

In the first of this blog trilogy, 'Are you listening,' I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. In the second, 'See no evil,' we bizarrely saw how Sir Francis Drake, Admiral Nelson and Clint Eastwood all had something in common with Mizaru, one of the 3 wise monkeys (Kikazaru and Iwazaru being the other two)... » read more

“See No Evil” Shouldn’t Apply To SoC Design
By Tim Penhale-Jones - 11 Jun, 2020 - Comments: 0

In the first part of this blog series, Talking Sense with Moortec…’Are you listening’, I looked at not waiting for hindsight to be wise after the event, instead make use of what’s available and act ahead of time. There’s a Japanese maxim, depicting three ‘wise’ monkeys… Kikazaru, Mizaru, and Iwazaru, better known as ‘hear no evil, see no evil and speak no evil’. If they we... » read more

New Approaches For Dealing With Thermal Problems
By Ann Mutschler - 11 Jun, 2020 - Comments: 0

New thermal monitoring, simulation and analysis techniques are beginning to coalesce in chips developed at leading-edge nodes and in advanced packages in order to keep those devices running at optimal temperatures. This is particularly important in applications such as AI, automotive, data centers and 5G. Heat can kill a chip, but it also can cause more subtle effects such as premature aging... » read more

Monitoring For In-Die Process Speed Detection
By Richard McPartland - 14 May, 2020 - Comments: 0

Chip designers working on advanced nodes typically include a fabric of sensors spread across the die for a number of very specific reasons. In this, the second of a three-part blog series, we explore some of the key applications and benefits of these types of sensing solutions. In this installment, the focus is In-Die Process Speed Detection and why understanding in-chip process speed detecti... » read more

Benefits Of In-Chip Thermal Sensing
By Richard McPartland - 22 Apr, 2020 - Comments: 0

The latest SoCs on advanced semiconductor nodes typically include a fabric of sensors spread across the die, and for good reason. But why and what are the benefits? This first blog of a three-part series explores some of the key applications for in-chip thermal sensing and why embedding in-chip monitoring IP is an essential step to maximize performance and reliability and minimize power, or a... » read more

The Future Of Embedded Monitoring, Part 1
By Stephen Crosher - 13 Feb, 2020 - Comments: 0

Shall I compare thee to a…Rolls Royce jet engine? ‘There is a new era dawning whereby deeply embedded sensing within all technology will bring about great benefit for the reliability and performance of semiconductor-based products.’ These were my words during a presentation to an industry audience in China back in September 2015. During that same presentation, somewhat to the consterna... » read more

Finding Hotspots In AI Chips
By Stephen Crosher - 14 Nov, 2019 - Comments: 0

Things are getting far more complicated as we move down to 7nm & 5nm but the tolerances of some of the physical effects that we have been measuring in the past are much tighter than they were at the older nodes. How do we track all that? What we see is that as we descend through the advanced nodes, say from 16nm down to 12nm, 7nm and more recently 5nm, we see that gate density starts to ... » read more

From Womb To Tomb: A Lifetime Of Chip Data In A Common Language
By Noam Brousard - 08 Oct, 2019 - Comments: 0

Every integrated circuit (IC) has a lifetime of stories to tell. From design through the end of a chip’s life, it can let us know what’s happening all along the way, providing we give it a voice and the language to do so. But until we can gain access to this data, the lives of these ICs remain secret. In-chip monitoring opens up those secrets. It helps to optimize performance, and it is esp... » read more

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