The Week In Review: Manufacturing

By Mark LaPedus - 04 Aug, 2017 - Comments: 0

Chipmakers The situation between Toshiba and its fab partner, Western Digital (WD), has gone from bad to worse. As reported, troubled Toshiba recently selected a group to buy its memory business. The consortium includes the Innovation Network Corp. of Japan, the Development Bank of Japan and Bain Capital. Rival SK Hynix is also part of the group. WD attempted but failed to buy the unit, an... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 30 Jun, 2017 - Comments: 0

Chipmakers Toshiba and its fab partner, Western Digital, have jointly rolled out a 96-layer 3D NAND product amid a legal dispute. The companies have developed prototype samples of a 96-layer 3D NAND device. Samples of the new 96-layer product, which is a 256 gigabit (32 gigabytes) device, is scheduled for release in the second half of 2017 and mass production is targeted for 2018. Separately, ... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 23 Jun, 2017 - Comments: 0

Chipmakers The NAND market is in flux. Not long ago, troubled Toshiba put its memory unit on the block. Finally, the company has selected a group to buy its memory business. The consortium includes the Innovation Network Corp. of Japan, the Development Bank of Japan and Bain Capital. Rival SK Hynix is also part of the group. Others attempted to bid on the business, including Western Digita... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Innovation Network Corp. of Japan

The Week In Review: Manufacturing

The Week In Review: Manufacturing

The Week In Review: Manufacturing

Trending Articles

NAND Flash Targets 1,000 Layers

One Chip Vs. Many Chiplets

FOPLP Gains Traction in Advanced Semiconductor Packaging

HBM Options Increase As AI Demand Soars

Asia Government Funding Surges

Knowledge Centers
Entities, people and technologies explored