tag: Intel

Making high-capacity data caches more efficient
By Technical Paper Link - 24 Oct, 2017 - Comments: 4

Source: Researchers from MIT, Intel, and ETH Zurich Xiangyao Yu (MIT), Christopher J. Hughes (Intel), Nadathur Satish (Intel) Onur Mutlu (ETH Zurich), Srinivas Devadas (MIT) Technical Paper link MIT News article As the transistor counts in processors have gone up, the relatively slow connection between the processor and main memory has become the chief impediment to improving comp... » read more

Manufacturing Bits: Oct. 24
By Mark LaPedus - 24 Oct, 2017 - Comments: 0

Redefining unit measurements At a recent meeting, the International Committee for Weights and Measures (CIPM) took the next step towards the expected redefinition of four base units within the International System of Units (SI). The SI base units include the following metrics or constants--meter, kilogram, second, ampere, kelvin, mole, and the candela. Here’s the fundamental constant... » read more

System Bits: Oct. 24
By Ann Mutschler - 24 Oct, 2017 - Comments: 0

Optical communication on silicon chips With the huge increase in computing performance in recent decades achieved by squeezing ever more transistors into a tighter space on microchips, at the same time this downsizing has also meant packing the wiring within microprocessors ever more tightly together. This has led to effects such as signal leakage between components, which can slow down commun... » read more

Searching For EUV Mask Defects
By Mark LaPedus - 19 Oct, 2017 - Comments: 2

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this technology can be used in production. One lingering issue that is becoming more worrisome is how to find [gettech id="31045" comment="EUV"] mask defects. That isn't the only issue, of course. The industry continues to work on the power source and resists. Bu... » read more

What’s Up With MEMS?
By Paula Doe - 19 Oct, 2017 - Comments: 0

New sensor technologies, and smarter ways of integrating more intelligence, continue to generate unexpected opportunities in the changing MEMS business. Changes needed for sensors for context awareness If digital assistants are ever going to be really useful, they’ll need some particular sensor capabilities to understand emotion, suggests Lama Nachman, head of Intel’s Anticipatory Compu... » read more

Next-Gen Mask Writer Race Begins
By Mark LaPedus - 19 Oct, 2017 - Comments: 5

Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

Memory Test Challenges, Opportunities
By Jeff Dorsch - 18 Oct, 2017 - Comments: 0

The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side. Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAM... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 13 Oct, 2017 - Comments: 0

Materials and equipment A scandal has rocked Japan’s Kobe Steel. The company disclosed that it has falsified inspection data for iron powder, aluminum and copper products that were sent to over 200 customers in the automotive, electronics, transportation and other sectors. The falsified data involves 20,000 tones of products, according to reports. Kobe apologized for the issues and provided ... » read more

Data Centers Turn To New Memories
By Ann Mutschler - 12 Oct, 2017 - Comments: 3

DRAM extensions and alternatives are starting to show up inside of data centers as the volume of data being processed, stored and accessed continues to skyrocket. This is having a big impact on the architecture of data centers, where the goal now is to move processing much closer to the data and to reduce latency everywhere. Memory has always been a key piece of the Von Neumann compute archi... » read more

Blog Review: Oct. 11
By Jesse Allen - 11 Oct, 2017 - Comments: 0

Mentor's Matthew Balance examines the separation of concerns between test intent and test realization in the Portable Stimulus specification. Synopsys' Deepak Nagaria checks out the features that makes LPDDR4 efficient in terms of power consumption, bandwidth utilization, data integrity and performance. Cadence's Meera Collier listens in as Chris Rowen considers whether AI processing shou... » read more

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