Advanced Lithography: Moore’s Law Moves On


Every February, experts in nano patterning technologies converge in San Jose, Calif., to present their road maps, brainstorms and results at the SPIE Advanced Lithography Symposium. This year, there was more confusion than ever, partly the result of sessions in unlabeled (but beautiful) new ballrooms at the Convention Center, but mostly because of industry divergences. There is no longer a s... » read more

Big Shift In SoC Verification


Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

The Week In Review: Manufacturing


SanDisk filed a civil suit against Korea’s SK Hynix. Additionally, SanDisk has submitted a criminal complaint with the Tokyo Metropolitan Police Department against a former employee. These actions relate to the theft of trade secrets related to NAND flash technology by a former engineer of SanDisk who left the company in 2008 to work for SK Hynix. Cadence Design Systems and GlobalFoundrie... » read more

Do We Need A “Glue” Engineer?


Design and verification are so complex today and fraught with market risk that it keeps managers awake and sweating at night. So much of design is carved up in IP blocks and subsystems, each with their own verification issues and methodologies. To manage the complexity the design is partitioned, and so too are the teams. But as software verification becomes more crucial to system-design succ... » read more

The Week In Review: Design


Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

The Week In Review: Manufacturing


The smartphone market is maturing and slowing down. Now, according to International Data Corp. (IDC), the total tablet market, inclusive of both tablets and 2-in-1 devices, is forecast to grow 19.4% in 2014, down from a growth rate of 51.6% in 2013. IDC also reduced the 2014 forecast by -3.6% from its previous projection to 260.9 million units worldwide. The reduction in the short-term forecast... » read more

Big Shift In SoC Verification


Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

Time to mend the EE / CS divide


There’s been a lot of news out the last few weeks about the future of our industry, and although these news flashes may seem unrelated, they are quite correlated. First, there was the disturbing news in Mark LaPedus’ article here on Semiconductor Engineering, “EUV Suffers New Setback,” portending a rough ride for the commercialization of EUV lithography. EUV will be needed to create ... » read more

Manufacturing Bits: Feb. 25


Intel joins DSA consortium Arkema, ASML, Intel and others have formed a new consortium in the emerging directed self-assembly (DSA) arena.The group, dubbed PLACYD, is a European funded consortium. Part of the Seventh Framework European Programme (FP7) and funded by ENIAC JU (European Technology Platform for Nanoelectronics), the project includes Arkema, CEA-Leti, STMicroelectronics, Intel,... » read more

EUV Suffers New Setback


ASML Holding’s initial, production-worthy extreme ultraviolet (EUV) lithography tool has suffered a setback during a recent trial run at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). TSMC disclosed the problem during a public presentation at the 2014 Advanced Lithography conference in San Jose, Calif. During the trial run at TSMC, the EUV source crashed due to a misalignment of the l... » read more

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