Wafer Warpage Evolution During Key Backside Power Delivery Network Fabrication Steps (Korea Univ., Georgia Tech)


A new technical paper titled "Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication" was published by researchers at Korea University and Georgia Institute of Technology. Abstract "As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs),... » read more

Challenges Grow For Creating Smaller Bumps For Flip Chips


New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more