tag: interconnect

Executive Insight: Sehat Sutardja
By Ed Sperling - 11 Jan, 2016 - Comments: 1

Sehat Sutardja, chairman and CEO of Marvell, sat down with Semiconductor Engineering to talk about new approaches for design and memory and why costs and time to market are forcing changes in Moore's Law. What follows are excerpts of that conversation. SE: What was behind your move into modular packaging? Sutardja: The cost of building chips is getting out of hand. As we make things more ... » read more

Overcoming The Design Bottleneck
By Brian Bailey - 12 Nov, 2015 - Comments: 0

SoCs control most advanced electronics these days and functionality, quality, power and security are a combination of both hardware and software. All throughout the development of today's complex systems, the memory hierarchy has remained the same—preserving the notion of a continuous computing paradigm. Today, that decision is leading to performance and power issues. There are several rea... » read more

2.5D Creeps Into SoC Designs
By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

The Interconnect Bottleneck
By Ann Mutschler - 28 May, 2015 - Comments: 0

With communications playing a crucial role in the design and performance of multi-core SoCs, various interconnect structures have been proposed as promising solutions to simplify and optimize SoC design. However, sometimes things don’t go as planned and the interconnect becomes the bottleneck. “Under high utilization cases the DRAM will be over-constrained with requests from all the a... » read more

Extending The Hardmask
By Mark LaPedus - 19 May, 2015 - Comments: 0

In chip production, the backend-of-the-line (BEOL) is where the critical interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips. “The scaling roadblocks that the interconnect faces need to ... » read more

The Week In Review: Design
By Ed Sperling - 27 Jun, 2014 - Comments: 0

Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

Locking Down The Chip
By Ernest Worthman - 05 Jun, 2014 - Comments: 1

The crypto processor is poised to break into the mainstream SoC world. Lower costs for manufacturing, coupled with rising security concerns from increased connectivity and growing complexity have cracked open the door on this approach to locking down a chip. Crypto processors aren’t a new concept, but they generally have been reserved for high-end applications. Until recently, they have ju... » read more

Manufacturing Bits: June 3
By Mark LaPedus - 03 Jun, 2014 - Comments: 0

World’s thinnest TFTs The U.S. Department of Energy’s Argonne National Laboratory has devised the world’s thinnest flexible, 2D thin-film transistors (TFTs). The transistors are just 10 atomic layers thick. TFTs are typically used in screens and displays. In the lab, Argonne researchers fabricated the TFTs on both a conventional silicon platform and a flexible substrate. [caption i... » read more

Executive Insight: Charles Janac
By Ed Sperling - 30 May, 2014 - Comments: 0

SE: What’s your biggest concern? Janac: Staying current. One of the things that is really important is to understand shifts in the marketplace. In the past, we looked at whether to target our interconnect solution at digital TV or mobility. This was actually a very interesting question in 2005. The DTV market looked better, but we were not getting enough evaluations. We were doing better i... » read more

Manufacturing Bits: May 27
By Mark LaPedus - 27 May, 2014 - Comments: 0

Chip printing process Fraunhofer Institute for Manufacturing Technology and Advanced Materials has developed a novel way to make systems using electronic components, such as resistors, transistors and capacitors. Researchers use simple printers and a robot-assisted production line. The components and other devices made from the technology could be used in various applications, such as digit... » read more

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