tag: IP

Experts At The Table: IP Integration Hurdles
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversatio... » read more

Bridging IP With Verification Standards
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

Talking Heads
By Ed Sperling - 21 Oct, 2010 - Comments: 0

The use of more third-party IP inside SoCs coupled with problems encountered at advanced process nodes is turning up some interesting challenges—and pointing the industry in some interesting directions. It’s a well-known fact that third-party IP isn’t always used as it was intended. Even internally developed IP isn’t always used as prescribed. It’s not unusual for chip developers t... » read more

Connecting The Pieces
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qual... » read more

Balancing Quality, Cost And Locale
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler As more features are packed into a single SoC there are simply more time-critical decisions to make. Instead of holding up one chip of a six-chip chipset, a delay or error on one chip can stop the whole parade. That explains why one of the most vibrant parts of the business at big EDA companies these days is standard IP, and why most of the other commercial IP make... » read more

New Math: 1+1=1?
By Ed Sperling - 07 May, 2010 - Comments: 0

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

Integrated IP Goes Vertical
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

Relocating Intelligence
By Ed Sperling - 23 Oct, 2009 - Comments: 0

For the past couple of decades, intelligence in a system was largely a function of the logic in a processor. That may change, given some of the disparate discussions now under way across the electronics industry. Putting all the intelligence in one place can make the design process more efficient, but it doesn’t necessarily make the system more efficient, either from a performance or pow... » read more

Tires That Talk
By Ed Sperling - 14 Sep, 2009 - Comments: 0

[youtube vid=JHxu-FWYxlw] » read more

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