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Chip Industry Week In Review

By The SE Staff - 03 May, 2024 - Comments: 0

Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry's gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea. UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC ... » read more

Chip Industry Week In Review

By The SE Staff - 26 Apr, 2024 - Comments: 0

President Biden announced four new Workforce Hubs to support the CHIPS Act and other initiatives, in Upstate New York, Michigan, Milwaukee, and Philadelphia. The White House also provided economic context and progress updates for the President’s workforce strategy. Samsung began mass production of its ninth-gen industry-first V-NAND chip. Along with one-terabit triple-level cell design, th... » read more

Chip Industry Week In Review

By The SE Staff - 03 Nov, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Trending Articles

EDA Looks Beyond Chips

System design, large-scale simulations, and AI/ML could open multi-trillion-dollar markets for tools, methodologies, and services.

Chip Industry Week In Review

Samsung, Synopsys' GAA processors; UMC's 3D IC process; Si wafer shipments down; SiC wafer processing equipment up; women in CHIPS Act projects; imec startup fund; Infineon, ETAS auto security collab; quantum error correction; Intel's cryogenic probing process.

by The SE Staff

Is There Any Hope For Asynchronous Design?

This approach has long held promise, but never managed to deliver. Is there a fundamental problem, or is it just bad luck?

by Brian Bailey

Chip Industry Week In Review

TSMC-SK hynix HBM4 deal; Intel's high-NA EUV; big haul for Micron, Samsung; Cadence's new emulation, prototyping systems; architecting chips for HPC; Japan, China's IC output; funding for metrology; advanced packaging electromigration.

by The SE Staff

Multi-Die Design Pushes Complexity To The Max

Continued scaling using advanced packaging will require changes across the entire semiconductor ecosystem.

by Ann Mutschler

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Entities, people and technologies explored

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The Rising Price Of Power In Chips

More data requires faster processing, which leads to a whole bunch of problems — not all of which are obvious or even solvable.

by Ed Sperling

Chiplet IP Standards Are Just The Beginning

Data and protocol interoperability standards are needed for EDA tools, and there are more hurdles ahead. Customized chiplets will be required for AI applications.

by Ann Mutschler

Electromigration Concerns Grow In Advanced Packages

Higher density, heat, and more materials make it harder to ensure reliability.

by Laura Peters

Silicon Photonics Manufacturing Ramps Up

The promise of photonics ICs is spurring innovation, but complex processes and a lack of open foundries are keeping it from reaching its full potential.

by Gregory Haley

Backside Power Delivery Gears Up For 2nm Devices

But this novel approach to optimizing logic performance depends on advancing lithography, etching, polishing, and bonding processes.

by Laura Peters

X-ray Inspection In The Semiconductor Industry

Utilizing multiple technologies helps create a more complete inspection picture.

by Chris Rand

SRAM Scaling Issues, And What Comes Next

While it will remain a workhorse memory, using SRAM at advanced nodes requires new approaches.

by Karen Heyman

What Works Best For Chiplets

Not all chiplets are interchangeable, and options will be limited.

by Anne Meixner

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