tag: Mentor Graphics

Insurance, Doctors And ESL
By Jon McDonald - 25 Mar, 2010 - Comments: 0

By Jon McDonald Return on investment is a subject that comes up frequently when people are thinking about adopting higher-level design approaches. After all, we are talking about adding work—we need to model, design, simulate and analyze the system. All of these tasks take time and cost money. So what are we getting in return? Before we can think about the return, we have to identify wha... » read more

New Forces For Consolidation
By Ed Sperling - 05 Mar, 2010 - Comments: 0

For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single... » read more

The Bright—And Much Larger—Future
By Ed Sperling - 01 Mar, 2010 - Comments: 0

The recent pushes by both Synopsys and Mentor into new markets should say something about the state of EDA. Being able to lay out the wires and subsystems on a chip, not to mention verifying that it all works, will always be vital to getting SoCs to tapeout. But that kind of work will not generate the kind of growth the big EDA companies are looking for—at least not without some major tweaks ... » read more

Expert Shootout: Parasitic Extraction
By Ed Sperling - 26 Feb, 2010 - Comments: 0

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: What changes with at 22nm and beyond with structures like FinFETs? Robertson: It’s no... » read more

Stop Texting Me
By Ed Sperling - 25 Feb, 2010 - Comments: 0

By Brian Fuller It was a simple request for a story: “You play around with this social-media stuff: Is it having an impact within engineering organizations?” My first thought was “social” and “engineer” should not be in the same sentence. Someone recently told me a story about trying—through Twitter no less—to set up a face-to-face meeting with an engineer at a live event.... » read more

Mind The Gap
By Ed Sperling - 25 Feb, 2010 - Comments: 0

By Ed Sperling Throughout system-level design there are gaps. High-level modeling doesn’t connect directly to RTL code. Synthesis and high-level synthesis remain worlds apart. There are even gaps in the expertise, from the people who handcraft RTL to those who take it for granted. Some of these gaps will get closed over time. Others will never be closed. In same cases it doesn’t matter.... » read more

Irrational Exuberance Meets High-Level Design
By Jon McDonald - 25 Feb, 2010 - Comments: 0

By Jon McDonald Irrational exuberance is running rampant. Design managers believe all their systems engineers and software programmers are going to be able to drive the hardware design process from a high-level description. OK, perhaps irrational exuberance is a bit strong and it may not be quite rampant, but I’ve heard statements recently both from customers and suppliers pushing in th... » read more

Still Room For Startups?
By Ed Sperling - 25 Feb, 2010 - Comments: 0

Can startups still survive in an increasingly complex, high up-front investment world? System-Level Design posed that question to Mentor Graphics, Synopsys, Oasys and an end user. [youtube vid=3RGvRnDGiTE] » read more

Expert Shootout: Parasitic Extraction
By Ed Sperling - 19 Feb, 2010 - Comments: 0

Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: Does parasitic extraction get more complex as we move into multicore chips? And if so, wh... » read more

Rethinking Test
By Ann Mutschler - 11 Feb, 2010 - Comments: 0

By Ann Steffora Mutschler The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail. This ‘false failure’ c... » read more

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