tag: Mentor Graphics

Timing Bomb
By Ed Sperling - 22 Apr, 2010 - Comments: 0

By Ed Sperling Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes. Systematic variability that was at least predictable at 90nm has become random at 45nm. Tools that worked fine with two corner cases now have to deal with hundreds. And as more functions make their way onto a single die, often with multiple modes of oper... » read more

Who’s Calling The Shots Now?
By Ann Mutschler - 22 Apr, 2010 - Comments: 0

By Ann Steffora Mutschler Determining who makes the decisions in semiconductor industry is not as easy as it sounds. There is not a straight line of responsibility in today’s market due to changing industry dynamics such as the shift from the IDM business model to the foundry model. “If you go back far enough, everyone had to manufacture their own chips. There was a substantial influenc... » read more

Why Your iPhone Battery Doesn’t Last
By Jon McDonald - 22 Apr, 2010 - Comments: 0

By Jon McDonald The other day a friend asked about the battery life on my iPhone. I love the phone by the way; he was disappointed with how often he had to recharge his. I responded with the one thing I had tried—turn off the Bluetooth. With that one change I have been pretty happy with the time between charges. His question got me thinking about the battery life of the phone, and I start... » read more

The Problem With Proximity
By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Ed Sperling At 90nm companies had to begin thinking seriously about how the signals inside a chip would begin interfering with each other. At 40nm and beyond, they have to consider how signals are interfering with each other across an entire device that may include multiple SoCs. This marks an interesting shift in what companies have been calling holistic design for the better part of a ... » read more

Killer Bugs
By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Ed Sperling Hardware and software bugs are all around us. When an application suddenly dies or a smart phone freezes because of the unanticipated interaction between hardware and software blocks in a system on chip, most users aren’t even the least bit fazed. They usually just re-boot and forget about it. Bugs caused by power are an entirely different matter, however. For one thing, ... » read more

Experts At The Table: Verification Nightmares
By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: What’s the big problem in ... » read more

Field Solvers To The Rescue
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Pallab Chatterjee Field solvers have always been part of the Parasitic Extraction (PEX) world, but due to their long run times and complexity in configuration, their role was relegated to the setup/reference table generation for the pattern based 1-D and 2-D RC extraction tools. That’s about to change. Mentor, in combination with STMicroelectronics, one of it customers, said that at ... » read more

Rounding Up Design Corners
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Pallab Chatterjee With advanced process development occupying the 32nm to 22nm corridor, production SoC and ASIC designs are being built at the 180nm to 45nm nodes. In these processes, the designer has to contend with cross-wafer variation and non-correlated design corners, as well as multiple operation states. This is referred to as multi-corner multi-mode (MCMM) and variation analysis. ... » read more

Emulation 2010
By Ann Mutschler - 25 Mar, 2010 - Comments: 0

By Ann Steffora Mutschler In an industry that was once fraught with patent infringement lawsuits, hostile takeovers and other exciting corporate warfare, the hardware-assisted emulation market has quieted down considerably. That doesn’t mean it has lost its luster, though. It still plays an integral, if not ever-increasing and expanding, role in the verification efforts of most semiconductor... » read more

Slow Adoption for ESL
By Brian Fuller - 25 Mar, 2010 - Comments: 0

By Brian Fuller It’s been more than a decade since electronic system level (ESL) abstraction started to gain traction in EDA. It’s been more than a few years since the industry began to plan for the day when the benefits of embracing C-language approaches to design description and validation would find designers churning out massively complex and profitable designs while sitting in lawn ch... » read more

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