tag: Mentor Graphics

Making DFM Work Better
By Ann Mutschler - 17 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase. There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital si... » read more

Synthesis: Next Steps In SoC Design
By Ed Sperling - 17 Dec, 2009 - Comments: 0

Five experts sound off to System-Level Design on the state of synthesis and what's needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executi... » read more

Experts At The Table: Rising Complexity Meets Verification
By Ed Sperling - 10 Dec, 2009 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are ... » read more

5 Reasons For Change
By Ed Sperling - 04 Dec, 2009 - Comments: 0

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their r... » read more

Experts At The Table: Rising Complexity Meets Verification
By Ed Sperling - 04 Dec, 2009 - Comments: 0

Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are excerpts of that ... » read more

More Choices But Less Design Freedom
By Ed Sperling - 19 Nov, 2009 - Comments: 0

By Ed Sperling “What if” is an indelible part of the lexicon of every SoC architect and design engineer from the front end of the design flow all the way to manufacturing, but while the terminology will persist for years to come the answers and the value of those answers are starting to change. Complexity, cost and the need for better integration have simultaneously increased the numb... » read more

An ESL Measurement Epiphany
By Jon McDonald - 19 Nov, 2009 - Comments: 0

By Jon McDonald Sometimes something becomes so simple and clear it’s shocking. I recently experienced such an epiphany. It started with a typical discussion on hardware software relationships and tradeoffs. How do you know what should be done in which? Realistically there is no automatic method to determine the proper partition. The best we can do is to propose a potential solution, the... » read more

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

Hypervisors For Managing Power
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Ed Sperling Hypervisors are headed for a new role inside of multicore chips—managing the various power islands in addition to the cores. A patent application filed by IBM, entitled “Method and syarstem for hypervisor based power management,” shows the company’s intention to use hypervisors for everything from monitoring power consumption rates to scaling power for individual core... » read more

Power Trip Advisor
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Geoffrey James There’s never been a greater demand for power-efficient silicon. As consumer electronic devices get smaller, with increased functionality, battery power becomes a premium resource. At the same time, “Green IT” is a major corporate trend, and the best way to be environmentally sensitive (while saving on energy costs) is to buy technology that ekes the maximum computing o... » read more

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